參數(shù)資料
型號(hào): ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 39/87頁
文件大小: 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
39 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Remark:
The buffer can be automatically validated or cleared by using the Buffer
Length register (see
Table 38
).
9.3.4
Buffer Length register (address: 1Ch)
This register determines the current packet size (DATACOUNT) of the indexed
endpoint FIFO. The bit allocation is given in
Table 38
.
The Buffer Length register is automatically loaded with the FIFO size, when the
Endpoint MaxPacketSize register is written (see
Table 42
). A smaller value can be
written when required. After a bus reset, the Buffer Length register is made zero.
IN endpoint:
When data transfer is performed in multiples of MaxPacketSize, the
Buffer Length register is not significant. This register is useful only when transferring
data that is not a multiple of MaxPacketSize. The following two examples
demonstrate the significance of the Buffer Length register.
Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register need not be filled. This is
because the transfer size is a multiple of MaxPacketSize, and the MaxPacketSize
packets will be automatically validated because the last packet is also of
MaxPacketSize.
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register should be filled with 62 bytes just
before the MCU writes the last packet of 62 bytes. This ensures that the last packet,
which is a short packet of 62 bytes, is automatically validated.
Use bit VENDP in the Control register if you are not using the Buffer Length register.
This is applicable only to PIO mode access.
OUT endpoint:
The DATACOUNT value is automatically initialized to the number of
data bytes sent by the host on each ACK.
Table 36:
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Data Port register: bit allocation
15
14
13
12
DATAPORT[15:8]
0
0
R/W
4
DATAPORT[7:0]
0
0
R/W
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 37:
Bit
15 to 8
7 to 0
Data Port register: bit description
Symbol
DATAPORT[15:8]
DATAPORT[7:0]
Description
data (upper byte)
data (lower byte)
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