參數(shù)資料
型號: ISP1583BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件頁數(shù): 56/87頁
文件大?。?/td> 420K
代理商: ISP1583BS
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
56 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.4.8
DMA Endpoint register (address: 58h)
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in
Table 75
.
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (2Ch) at any time. Doing so would result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If
the DMA Endpoint register, however, is pointed to an active endpoint, the firmware
must not reference the same endpoint on the Endpoint Index register.
9.4.9
DMA Strobe Timing register (address: 60h)
This 1-byte register controls the strobe timing for MDMA mode, when bits
DMA_MODE in the DMA Configuration register have been set to 03h.
The bit allocation is given in
Table 77
.
Bit
Symbol
7
6
5
4
3
2
1
0
reserved
IE_
READ_1F0
0
0
R/W
IE_BSY_
DONE
0
0
R/W
IE_TF_
RD_DONE
0
0
R/W
IE_CMD_
INTRQ_OK
0
0
R/W
reserved
Reset
Bus reset
Access
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
Table 75:
Bit
Symbol
Reset
Bus reset
Access
DMA Endpoint register: bit allocation
7
6
5
4
3
2
1
0
reserved
EPIDX[2:0]
0
0
R/W
DMADIR
0
0
R/W
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
R/W
R/W
Table 76:
Bit
7 to 4
3 to 1
0
DMA Endpoint register: bit description
Symbol
Description
-
reserved
EPIDX[2:0]
selects the indicated endpoint for DMA access
DMADIR
0 —
Selects the RX/OUT FIFO for DMA read transfers
1 —
Selects the TX/IN FIFO for DMA write transfers.
Table 77:
Bit
Symbol
Reset
Bus reset
Access
DMA Strobe Timing register: bit allocation
7
6
reserved
-
-
-
-
R/W
R/W
5
4
3
2
1
0
DMA_STROBE_CNT[4:0]
1
1
R/W
R/W
-
-
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
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