參數資料
型號: ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數: 35/158頁
文件大?。?/td> 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
35 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0
8.2.2
USBSTS register (R/W: 0024h)
The USB Status (USBSTS) register indicates pending interrupts and various states of the
Host Controller. The status resulting from a transaction on the serial bus is not indicated in
this register. Software clears the register bits by writing ones to them. The bit allocation is
given in
Table 17
.
Table 15:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
USBCMD register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
1
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
0
0
0
0
0
R/W
7
LHCR
0
R/W
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
RS
0
R/W
reserved
[1]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 16:
Bit
31 to 8
7
USBCMD register: bit description
Symbol
Description
[1]
-
reserved
LHCR
Light Host Controller Reset
(optional): If implemented, it allows the
driver software to reset the EHCI controller without affecting the state of
the ports or the relationship to the companion Host Controllers. If not
implemented, a read of this field will always return logic 0.
-
reserved
RS
Run/Stop
: 1 = Run, 0 = Stop. When set, the Host Controller executes the
schedule.
6 to 1
0
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