參數(shù)資料
型號: ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 57/158頁
文件大?。?/td> 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
57 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
8.4.7
INT IRQ MASK AND register (R/W: 0328h)
Each bit of this register (see
Table 61
) corresponds to one of the 32 INT PTDs defined,
and is a hardware IRQ mask for each PTD done map. For details, see
Section 7.4
.
8.4.8
ATL IRQ MASK AND register (R/W: 032Ch)
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Section 7.4
.
Table 62
shows the bit description of the register.
8.5 Philips Transfer Descriptor
The standard EHCI data structures as described in Enhanced Host Controller Interface
Specification for Universal Serial Bus Rev. 1.0 are optimized for the bus master operation
that is managed by the hardware state machine.
The PTD structures of the ISP1761 are translations of the EHCI data structures that are
optimized for the ISP1761, while keeping the architecture of the EHCI data structures the
same. This is because the ISP1761 is a slave Host Controller and has no bus master
capability.
Table 60:
Bit
31 to 0 ISO_IRQ_
MASK_
AND[31:0]
ISO IRQ MASK AND register: bit description
Symbol
Access
Value
R/W
0000 0000h
ISO IRQ Mask AND
: Represents a direct map for
ISO PTDs 31 to 0.
0 —
No AND condition defined between ISO PTDs
1 —
The bits corresponding to certain PTDs are set
to logic 1 to define a certain AND condition between
the 32 INT PTDs.
Description
Table 61:
Bit
31 to 0 INT_IRQ_
MASK_
AND[31:0]
INT IRQ MASK AND register: bit description
Symbol
Access
Value
R/W
0000 0000h
Description
INT IRQ Mask AND
: Represents a direct map for
INT PTDs 31 to 0.
0 —
No OR condition defined between INT PTDs
1 —
The bits corresponding to certain PTDs are set
to logic 1 to define a certain AND condition
between the 32 INT PTDs.
Table 62:
Bit
31 to 0 ATL_IRQ_
MASK_
AND[31:0]
ATL IRQ MASK SAND register: bit description
Symbol
Access Value
R/W
0000 0000h
Description
ATL IRQ Mask AND
: Represents a direct map for
ATL PTDs 31 to 0.
0 —
No OR condition defined between ATL PTDs
1 —
The bits corresponding to certain PTDs are
set to logic 1 to define a certain AND condition
between the 32 ATL PTDs.
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