參數(shù)資料
型號: ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 80/158頁
文件大?。?/td> 724K
代理商: ISP1761
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8.5.6
Start and complete split for interrupt
Table 73
shows the bit allocation of start and complete split for interrupt
6
.
9
P
R
8
P
I
H
[1]
Reserved.
[2]
EndPt[0].
6.
Patent-pending: Start and complete split for interrupt.
Table 73:
Bit
DW7
DW5
DW3
Start and complete split for interrupt: bit allocation
62
61
60
59
58
57
63
56
55
54
53
52
reserved
INT_IN_1[7:0]
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
INT_IN_7[7:0]
μ
SCS[7:0]
INT_IN_2[7:0]
B
X
INT_IN_0[7:0]
A
H
S
C
[1]
D
T
Cerr
[1:0]
reserved
NrBytesTransferred[11:0] (4 kB for full-speed and
low-speed)
Token
[1:0]
DW1
HubAddress[6:0]`
PortNumber[6:0]
SE[1:0]
-
S
EP
Type
[1:0]
13
INT_IN_4[7:0]
Status1
[2:0]
DeviceAddress[6:0]
EndPt
[3:0]
Bit
DW6
DW4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
12
11
10
9
8
7
6
5
4
3
2
1
0
INT_IN_6[7:0]
Status6
INT_IN_5[7:0]
Status4
[2:0]
INT_IN_3[7:0]
μ
SA[7:0]
Status7
[2:0]
[2:0]
Status5
[2:0]
Status3
[2:0]
Status2
[2:0]
Status0
[2:0]
DW2
reserved
DataStartAddress[15:0]
μ
Frame[7:0] (full-speed and
low-speed)
DW0
[2]
[1]
MaxPacketLength[10:0]
NrBytesToTransfer[14:0] (4 kB for full-speed and low-speed)
[1]
V
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