參數(shù)資料
型號(hào): ISP1761BE,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 160/164頁
文件大?。?/td> 767K
代理商: ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
94 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
To use port 1 as a host controller, write 0080 0018h to this register after power-on. To use port 1 as a
peripheral controller, write 0006 0400h to this register after power-on.
9.5.3 OTG Interrupt registers
9.5.3.1
OTG Status register
This register indicates the current state of the signals that can generate an interrupt. The
bit allocation of the register is given in Table 86.
[1]
The reset value depends on the corresponding OTG status. For details, see Table 87.
2
DM_PULLDOWN
DM pull-down:
0 — Disable
1 — Enable
1
DP_PULLDOWN
DP pull-down:
0 — Disable
1 — Enable
0
DP_PULLUP
0 — The pull-up resistor is disconnected from the DP line. The data
line pulsing is stopped.
1 — An internal 1.5 k
pull-up resistor is present on the DP line.
The data line pulsing is started.
Remark: When port 1 is in peripheral mode or it plays the role of a
peripheral while the OTG functionality is enabled, it depends on the
setting of DP_PULLUP and the VBUS sensing signal to connect the
DP line to HIGH through a pull-up resister. VBUS is an internal signal.
When 5 V is present on the VBUS pin, VBUS = 1.
Table 85.
OTG Control register (address set: 0374h, clear: 0376h) bit description …continued
Bit[1]
Symbol
Description
Table 86.
OTG Status register (address 0378h) bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
B_SE0_
SRP
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
B_SESS_
END
reserved
RMT_
CONN
ID
DP_SRP
A_B_SESS
_VLD
VBUS_VLD
Reset
000
0
Access
RRRRRRRR
Table 87.
OTG Status register (address 0378h) bit description
Bit
Symbol
Description
15 to 9
-
reserved for future use
8
B_SE0_SRP
2 ms of SE0 detected in the B-idle state
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