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| 型號(hào)： | ISP1761BE,518 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128 |
| 文件頁(yè)數(shù)： | 75/164頁(yè) |
| 文件大?。?/td> | 767K |
| 代理商： | ISP1761BE,518 |
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ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
17 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
The total amount of memory allocated to the payload determines the maximum transfer
size specied by a PTD, a larger internal memory size results in less CPU interruption for
transfer programming. This means less time spent in context switching, resulting in better
CPU usage.
A larger buffer also implies that a larger amount of data can be transferred. This transfer,
however, can be done over a longer period of time, to maintain the overall system
performance. Each transfer of the USB data on the USB bus can span up to a few
milliseconds before requiring further CPU intervention for data movement.
The internal architecture of the ISP1761 allows a exible denition of the memory buffer
for optimization of the data transfer on the CPU extension bus and the USB. It is possible
to implement different data transfer schemes, depending on the number and type of USB
devices present. For example: push-pull; data can be written to half of the memory while
data in the other half is being accessed by the host controller and sent on the USB bus.
This is useful especially when a high-bandwidth ‘continuous or periodic’ data ow is
required.
Through an analysis of the hardware and software environment regarding the usual data
ow and performance requirements of most embedded systems, NXP has determined the
optimal size for the internal buffer as approximately 64 kB.
7.2.2 Structure of the ISP1761 host controller memory
The 63 kB of internal memory consists of the PTD area and the payload area.
The PTD memory zone is divided into three dedicated areas for each main type of USB
transfer: Isochronous (ISO), Interrupt (INT) and Asynchronous Transfer List (ATL). As
shown in Table 4, the PTD areas for ISO, INT and ATL are grouped at the beginning of the
memory, occupying the address range 0400h to 0FFFh, following the register address
space. The payload or data area occupies the next memory address range 1000h to
FFFFh, meaning that 60 kB of memory are allocated for the payload data.
A maximum of 32 PTD areas and their allocated payload areas can be dened for each
type of transfer. The structure of a PTD is similar for every transfer type and consists of
eight Double Words (DWs) that must be correctly programmed for a correct USB data
transfer. The reserved bits of a PTD must be set to logic 0. A detailed description of the
PTD structure can be found in Section 8.5.
The transfer size specied by the PTD determines the contiguous USB data transfer that
can be performed without any CPU intervention. The respective payload memory area
must be equal to the transfer size dened. The maximum transfer size is exible and can
be optimized, depending on the number and nature of USB devices or PTDs dened and
their respective MaxPacketSize.
The CPU will program the DMA to transfer the necessary data in the payload memory.
The next CPU intervention will be required only when the current transfer is completed
and DMA programming is necessary to transfer the next data payload. This is normally
signaled by the IRQ that is generated by the ISP1761 on completing the current PTD,
meaning all the data in the payload area was sent on the USB bus. The external IRQ
signal is asserted according to the settings in the IRQ Mask OR or IRQ MASK AND
registers, see Section 8.4.
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| ISP1761BEGE | 功能描述:IC USB CTRL HI-SPEED 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1761BE-S | 功能描述:IC USB CONTROLLER 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1761BE-T | 功能描述:USB 接口集成電路 USB HS OTG CNTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BEUM | 功能描述:IC USB OTG CONTROLLER HS 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1761ET | 功能描述:USB 接口集成電路 USB 2.0 HS OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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