參數(shù)資料
型號： ISP1761BE,518
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 30/164頁
文件大?。?/td> 767K
代理商： ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
124 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
Bit
7
6
5
4
3
2
1
0
Symbol
VBUS
DMA
HS_STAT
RESUME
SUSP
PSOF
SOF
BRESET
Reset
00000000
Bus reset
0000000
unchanged
Access
R/W
Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit
description
Bit
Symbol
Description
31 to 26
-
reserved
25
EP7TX
Logic 1 indicates the endpoint 7 TX buffer as interrupt source.
24
EP7RX
Logic 1 indicates the endpoint 7 RX buffer as interrupt source.
23
EP6TX
Logic 1 indicates the endpoint 6 TX buffer as interrupt source.
22
EP6RX
Logic 1 indicates the endpoint 6 RX buffer as interrupt source.
21
EP5TX
Logic 1 indicates the endpoint 5 TX buffer as interrupt source.
20
EP5RX
Logic 1 indicates the endpoint 5 RX buffer as interrupt source.
19
EP4TX
Logic 1 indicates the endpoint 4 TX buffer as interrupt source.
18
EP4RX
Logic 1 indicates the endpoint 4 RX buffer as interrupt source.
17
EP3TX
Logic 1 indicates the endpoint 3 TX buffer as interrupt source.
16
EP3RX
Logic 1 indicates the endpoint 3 RX buffer as interrupt source.
15
EP2TX
Logic 1 indicates the endpoint 2 TX buffer as interrupt source.
14
EP2RX
Logic 1 indicates the endpoint 2 RX buffer as interrupt source.
13
EP1TX
Logic 1 indicates the endpoint 1 TX buffer as interrupt source.
12
EP1RX
Logic 1 indicates the endpoint 1 RX buffer as interrupt source.
11
EP0TX
Logic 1 indicates the endpoint 0 data TX buffer as interrupt source.
10
EP0RX
Logic 1 indicates the endpoint 0 data RX buffer as interrupt source.
9
-
reserved
8
EP0SETUP
Logic 1 indicates that a SETUP token was received on endpoint 0.
7
VBUS
Logic 1 indicates a transition from LOW to HIGH on VBUS.
When implementing a pure host or peripheral, the OTG_DISABLE bit in
the OTG Control register (374h) must be set to logic 1 so that the VBUS
bit is updated with the correct value.
6
DMA
DMA status: Logic 1 indicates a change in the DMA Interrupt Reason
register.
5
HS_STAT
High-Speed Status: Logic 1 indicates a change from full-speed to
high-speed mode (HS connection). This bit is not set when the system
goes into the full-speed suspend.
4
RESUME
Resume status: Logic 1 indicates that a status change from suspend
to resume (active) was detected.
3
SUSP
Suspend status: Logic 1 indicates that a status change from active to
suspend was detected on the bus.
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