參數(shù)資料
型號: ISP1761BE,518
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 138/164頁
文件大?。?/td> 767K
代理商: ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
74 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 71.
Start and complete split for bulk: bit description
Bit
Symbol
Access
Value
Description
DW7
63 to 32
reserved
-
DW6
31 to 0
reserved
-
DW5
63 to 32
reserved
-
DW4
31 to 6
reserved
-
5J
SW — writes
-
0 — To increment the PTD pointer.
1 — To enable the next PTD branching.
4 to 0
NextPTDPointer[4:0] SW — writes
-
Next PTD Pointer: Next PTD branching assigned by the PTD
pointer.
DW3
63
A
SW — sets
HW — resets
-
Active: Write the same value as that in V.
62
H
HW — writes
-
Halt: This bit corresponds to the Halt bit of the Status eld of
TD.
61
B
HW — writes
-
Babble: This bit corresponds to the Babble Detected bit in the
Status eld of iTD, siTD or TD.
1 — when babbling is detected, A and V are set to 0.
60
X
HW — writes
-
Transaction Error: This bit corresponds to the Transaction
Error bit in the status eld.
SW — writes
-
0 — Before scheduling
59
SC
SW — writes 0
HW — updates
-
Start/Complete:
0 — Start split
1 — Complete split
58
reserved
-
57
DT
HW — writes
SW — writes
-
Data Toggle: Set the Data Toggle bit to start for the PTD.
56 to 55
Cerr[1:0]
HW — updates
SW — writes
-
Error Counter: This eld contains the error count for
asynchronous start and complete split (SS/CS) TD. When an
error has no response or bad response, Cerr[1:0] will be
decremented to zero and then Valid will be set to zero. A NAK
or NYET will reset Cerr[1:0]. For details, refer to
If retry has insufcient time at the beginning of a new SOF, the
rst PTD must be this retry. This can be accomplished if
aperiodic PTD is not advanced.
54 to 51
NakCnt[3:0]
HW — writes
SW — writes
-
NAK Counter: The V bit is reset if NakCnt decrements to zero
and RL is a non-zero value. Not applicable to isochronous split
transactions.
50 to 47
reserved
-
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