參數(shù)資料
型號: ISP1761BE,518
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 35/164頁
文件大?。?/td> 767K
代理商: ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
12 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
CS_N
106
A12
I
chip select assertion indicates the ISP1761 being accessed; active
LOW
input, 3.3 V tolerant
RD_N
107
B12
I
read enable; active LOW
input, 3.3 V tolerant
WR_N
108
B11
I
write enable; active LOW
input, 3.3 V tolerant
GNDD
109
A11
-
digital ground
BAT_ON_N
110
C10
OD
to indicate the presence of a minimum 3.3 V on pins 6 and 7
(open-drain); connect to VCC(I/O) through a 10 k pull-up resistor
output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant
DC_IRQ
111
A10
O
peripheral controller interrupt signal
output 4 mA drive, 3.3 V tolerant
HC_IRQ
112
B10
O
host controller interrupt signal
output 4 mA drive, 3.3 V tolerant
DC_DREQ
113
A9
O
DMA controller request for the peripheral controller
output 4 mA drive, 3.3 V tolerant
HC_DREQ
114
B9
O
DMA controller request for host controller
output 4 mA drive, 3.3 V tolerant
VCC(I/O)
115
C8
P
digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling
capacitor; see Section 7.7
HC_DACK
116
A8
I
host controller DMA request acknowledgment; when not in use,
connect to VCC(I/O) through a 10 k pull-up resistor
input, 3.3 V tolerant
DC_DACK
117
B8
I
peripheral controller DMA request acknowledgment; when not in
use, connect to VCC(I/O) through a 10 k pull-up resistor
input, 3.3 V tolerant
REG1V8
118
B7
P
core power output (1.8 V); internal 1.8 V for the digital core; used for
decoupling; connect a 100 nF capacitor; for details on additional
capacitor placement, see Section 7.7
HC_SUSPEND
/WAKEUP_N
119
A7
I/OD
host controller suspend and wake-up; 3-state suspend output
(active LOW) and wake-up input circuits are connected together
HIGH = output is 3-state; the ISP1761 is in suspend mode
LOW = output is LOW; the ISP1761 is not in suspend mode
connect to VCC(I/O) through an external 10 k pull-up resistor
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
DC_SUSPEND
/WAKEUP_N
120
C6
I/OD
peripheral controller suspend and wake-up; 3-state suspend output
(active LOW) and wake-up input circuits are connected together
HIGH = output is 3-state; the ISP1761 is in suspend mode
LOW = output is LOW; the ISP1761 is not in suspend mode
connect to VCC(I/O) through an external 10 k pull-up resistor
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
GNDC
121
A6
-
core ground
Table 2.
Pin description …continued
Symbol[1][2]
Pin
Type[3]
Description
LQFP128
TFBGA128
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