參數(shù)資料
型號: ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 124/158頁
文件大?。?/td> 724K
代理商: ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
124 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.7.4
DcScratch register (R/W: 0278h)
This 16-bit register can be used by the firmware to save and restore information. For
example, the peripheral status before it enters the suspend state. The content of this
register will not be altered by a bus reset. The bit allocation is given in
Table 142
.
10.7.5
Unlock Device register (W: 027Ch)
To protect the registers from getting corrupted when the ISP1761 goes into suspend, the
write operation is disabled if the PWRON bit in the Mode register is set to logic 0. In this
case, when the chip resumes, the Unlock Device command must be first issued to this
register before attempting to write to the rest of the registers. This is done by writing
unlock code (AA37h) to this register.
The bit allocation of the Unlock Device register is given in
Table 144
.
Table 142: DcScratch register: bit allocation
Bit
15
Symbol
Reset
0
Bus reset
Access
R/W
Bit
7
Symbol
Reset
0
Bus reset
Access
R/W
14
13
12
11
10
9
8
SFIRH[7:0]
0
0
0
0
0
0
0
unchanged
R/W
4
SFIRL[7:0]
0
unchanged
R/W
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 143: DcScratch register: bit description
Bit
Symbol
15 to 8
SFIRH[7:0]
7 to 0
SFIRL[7:0]
Description
Scratch firmware information register (higher byte)
Scratch firmware information register (lower byte)
Table 144: Unlock Device register: bit allocation
Bit
15
Symbol
Reset
Bus reset
Access
W
Bit
7
Symbol
Reset
Bus reset
Access
W
14
13
12
11
10
9
8
ULCODE[15:8] = AAh
not applicable
not applicable
W
4
ULCODE[7:0] = 37h
not applicable
not applicable
W
W
6
W
5
W
3
W
2
W
1
W
0
W
W
W
W
W
W
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