參數(shù)資料
型號: ISP1761BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 13/158頁
文件大小: 724K
代理商: ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
13 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals.
[2]
I = input only; O = output only; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output; AI = analog input;
P = power; (AI/O)(I) = analog input/output digital input; AI/I = analog input digital input.
DC_SUSPEND
/WAKEUP_N
120
C6
I/OD
Peripheral Controller suspend and wake-up; three-state suspend
output (active LOW) and wake-up input circuits are connected
together
HIGH = output is three-state; ISP1761 is in suspend mode
LOW = output is LOW; ISP1761 is not in suspend mode.
connect to V
CC(I/O)
through an external 10 k
pull-up resistor
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
core ground
external power-up reset; active LOW
input, 3.3 V tolerant
Remark:
During reset, ensure that all the input pins to the ISP1761
are not toggling.
analog ground
charge pump capacitor input; connect a 220 nF capacitor between
this pin and pin 125
charge pump capacitor input; connect a 220 nF capacitor between
this pin and pin 124
charge pump input; connect to 3.3 V
This pin has multiple functions:
Port 1 OC1_N detection when port 1 is configured for host
functionality and an external power switch is used; connect to
V
CC(I/O)
through a 10 k
resistor
V
BUS
out when internal charge pump is used and port 1 is
configured for the host functionality; maximum 50 mA current
capability; only for port 1
V
BUS
input detection when port 1 is defined for the peripheral
functionality.
input, 3.3 V tolerant
port 2 analog (5 V input) and digital overcurrent input; if not used,
connect to V
CC(I/O)
through a 10 k
resistor
input, 3.3 V tolerant
GND
RESET_N
121
122
A6
B6
-
I
GND
C_B
123
124
B5
A5
-
AI/O
C_A
125
B4
AI/O
V
CC(C_IN)
OC1_N/V
BUS
126
127
A4
B3
P
(AI/O)(I)
OC2_N
128
A3
AI/I
Table 2:
Symbol
[1]
Pin description
…continued
Pin
LQFP128
Ball
TFBGA128
Type
[2]
Description
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