參數(shù)資料
型號(hào)： ISP1761BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus On-The-Go controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 52/158頁
文件大?。?/td> 724K
代理商： ISP1761BE
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
52 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
For a 32-bit operation, the default wake-up counter value is 10
μ
s. For a 16-bit operation, the wake-up
counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.
8.4 Interrupt registers
8.4.1
HcInterrupt register (R/W: 0310h)
The bits of this register indicate the interrupt source, defining the events that determined
the INT generation. Clearing the bits that were set because of the events listed is done by
writing back logic 1 to the respective position. All bits must be reset before enabling new
interrupt events. These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN
in the HW Mode Control register.
Table 53
shows the bit allocation of the HcInterrupt
register.
2
OC2_PWR
OC2_N Powered
: Controls the powering of the overcurrent detection
circuitry for port 2.
0 —
Overcurrent detection is powered on or enabled during suspend
1 —
Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system
is in standby.
OC1_N Powered
: Controls the powering of the overcurrent detection
circuitry for port 1.
0 —
Overcurrent detection is powered on or enabled during suspend
1 —
Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system
is in standby.
Host Controller Clock Enabled
: Controls internal clocks during
suspend.
0 —
Clocks are disabled during suspend. This is the default value.
Only the LazyClock of 100 kHz
±
40 % will be left running in suspend if
this bit is logic 0. If clocks are stopped during suspend, CLKREADY
IRQ will be generated when all clocks are running stable.
1 —
All clocks are enabled even in suspend.
1
OC1_PWR
0
HC_CLK_
EN
Table 52:
Bit
[1]
Power Down Control register: bit description
…continued
Symbol
Description
Table 53:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterrupt register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
R/W
OTG_IRQ
0
R/W
ISO_IRQ
0
R/W
ATL_IRQ
0
R/W
0
0
0
0
R/W
R/W
R/W
R/W
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