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參數(shù)資料
| 型號(hào)： | ISPLSI 2096VE-200LT128 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 96I/O 4.5NS 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispLSI® 2000VE |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 4.5ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 24 |
| 宏單元數(shù)： | 96 |
| 門數(shù)： | 4000 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI2096VE-200LT128 |
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Specifications ispLSI 2096VE
11
Pin Description
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
NAME
Table 2-0002-2096VE
TQFP PIN NUMBERS
DESCRIPTION
21,
27,
35,
41,
51,
57,
64,
71,
85,
91,
99,
105,
115,
121,
128,
7,
19
48
77
14
15
112
20
22,
28,
36,
42,
52,
58,
65,
72,
86,
92,
100,
106,
116,
122,
1,
8,
80,
17
23,
29,
37,
43,
53,
59,
67,
73,
87,
93,
101,
107,
117,
123,
3,
9,
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
24,
30,
38,
44,
54,
60,
68,
74,
88,
94,
102,
108,
118,
124,
4,
10,
25,
32,
39,
45,
55,
61,
69,
75,
89,
96,
103,
109,
119,
125,
5,
11,
26
33
40
46
56
62
70
76
90
97
104
110
120
126
6
12
18,
111,
34,
127
50,
63,
2,
95,
16,
114
31,
47,
66,
81,
79,
98,
Global Output Enables input pins.
GOE 0, GOE 1
GND
V
VCC
CC
Ground (GND)
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
Active Low (0) Reset pin which resets all of the registers in the device.
RESET
Y0, Y1, Y2
13,
49,
82
No Connect.
NC1
TDI/IN 0
BSCAN
TMS/IN 1
113
84,
78
83,
Dedicated input pins to the device.
IN 4, IN 5
TDO/IN 2
TCK/IN 3
Output/Input — This pin performs two functions. When
BSCAN is logic
low, it functions as an output pin to read serial shift register data. When
BSCAN is high, it functions as a dedicated input pin.
Input — Dedicated in-system programming Boundary Scan enable input
pin. This pin is brought low to enable the programming mode. The TMS,
TDI, TDO and TCK controls become active.
Input — This pin performs two functions. When
BSCAN is logic low, it
functions as a serial data input pin to load programming data into the
device. When
BSCAN is high, it functions as a dedicated input pin.
Input — This pin performs two functions. When
BSCAN is logic low, it
functions as a mode control pin for the Boundary Scan state machine.
When
BSCAN is high, it functions as a dedicated input pin.
Input — This pin performs two functions. When
BSCAN is logic low, it
functions as a clock pin for the Boundary Scan state machine. When
BSCAN is high, it functions as a dedicated input pin.
1. NC pins are not to be connected to any active signal, VCC or GND.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2096VE-200LT128 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2096VE-250LT128 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2096VE-250LTN128 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2096VL | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2096VL-100LT128 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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