Specifications ispLSI 5512VE 8 Global Clock Distribution The ispLSI 5000VE Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input " />
參數(shù)資料
型號: ISPLSI 5512VE-80LF388I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 24/25頁
文件大?。?/td> 0K
描述: IC PLD ISP 256I/O 12NS 388FPBGA
標(biāo)準(zhǔn)包裝: 60
系列: ispLSI® 5000VE
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 12.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 16
宏單元數(shù): 512
門數(shù): 24000
輸入/輸出數(shù): 256
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 388-BBGA
供應(yīng)商設(shè)備封裝: 388-FPBGA(23x23)
包裝: 托盤
其它名稱: ISPLSI5512VE-80LF388I
Specifications ispLSI 5512VE
8
Global Clock Distribution
The ispLSI 5000VE Family has four dedicated clock input
pins: CLK0 - CLK3. CLK0 input is used as the dedicated
master clock that has the lowest internal clock skew with
no clock inversion to maintain the fastest internal clock
speed. The clock inversion is available on the remaining
CLK1 - CLK3 signals. By sharing the pins with the I/O
pins, CLK2 and CLK3 can not only be inverted but are
also available for logic implementation through GRP
signal routing. Figure 5 shows these different clock
distribution options.
Figure 5. ispLSI 5000VE Global Clock Structure
CLK0
CLK1
CLK 0
(dedicated pin)
CLK 1
(dedicated pin)
IO/CLK 2
(shared pin)
IO/CLK 3
(shared pin)
CLK2
CLK3
to/from GRP
Global Reset
RESET
(dedicated pin)
to/from GRP
IO0/TOE
(shared pin)
TOE
to/from GRP
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ISPLSI5512VE-80LF388I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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