![](http://datasheet.mmic.net.cn/30000/MQ80C32-12SBR_datasheet_2377008/MQ80C32-12SBR_75.png)
75
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
11. External Interrupts
The External Interrupts are triggered by the INT3:0 pins. Observe that, if enabled, the interrupts will trigger even if
the INT3:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The
External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the spec-
ification for the External Interrupt Control Registers – EICRA (INT3:0). When the external interrupt is enabled and
is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of fall-
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held
for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled
twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 s (nominal) at 5.0V and 25
C.
page 283. The MCU will wake up if the input has the required level during this sampling or if it is held until the end
the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start-up time, the
MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU
to complete the wake up to trigger the level interrupt.
11.0.1
External Interrupt Control Register A – EICRA
Bits 7..0 – ISC31, ISC30 – ISC01, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding
interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined
in
Table 11-1. Edges on INT3..INT0 are registered asynchronously.The value on the INT3:0 pins are sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will gen-
erate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency
can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level
must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level
triggered interrupt will generate an interrupt request as long as the pin is held low.
Note:
1. n = 3, 2, 1 or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the
EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Bit
76543210
ISC31
ISC30
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
EICRA
Read/Write
R/W
Initial Value
00000000
Table 11-1.
Interrupt Sense Contro
l(1)ISCn1
ISCn0
Description
0
The low level of INTn generates an interrupt request.
0
1
Any logical change on INTn generates an interrupt request
1
0
The falling edge between two samples of INTn generates an interrupt request.
1
The rising edge between two samples of INTn generates an interrupt request.