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參數(shù)資料
| 型號(hào)： | IXLD02SI |
| 廠商： | IXYS Corporation |
| 英文描述： | Differential 2A Ultra Fast Laser Diode Driver |
| 中文描述： | 差分甲超快速激光二極管驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | IXLD02SI |
3
IXLD02SI
Name
VDD Logic supply input voltage
VDDA Analog bias supply input voltage
VTT Internal bias voltage input
R
VTT
VTT terminal resistance
Definition
Min
4.5
4.5
2
30
Typ
VDDA/2
50
Max
5.5
5.5
3
70
Units
V
V
V
Kohms Measured with VDDin=VDDA=0V.
Test Conditions
Measured with Zin>10meg DVM.
I
IBI
Internal bias current input range
10
100
300
uA
External current source between
VDDA and IBI terminal.
I
IBI
=100uA.
External current source between
VDDA and IPW terminal.
I
IPW
=100uA.
I
IBI
=400uA, I
IPW
=300uA, I
IOP
=1mA.
mA External current source between
VDDA and IBI terminals.
V
IBI=100uA.
V
IBI
I
IPW
Measured IBI terminal voltage
Pulse width programming current input
range.
V
IPW
Measured IPW terminal voltage
t
PW
I
OUT
=2A peak,
Output current pulse width
I
IOP
OUT and OUTB output current, I
OUT
,
programming current.
V
IOP
Measured IOP terminal voltage
I
OUT
/I
IOP
Output current to programming current gain
0.6
-1
1.7
400
V
uA
100
0.6
1.7
3
V
ns
1
1
0
0.6
1.7
1800
2000
2200
I/I
I
IOP
=1mA, V
OUT
=V
OUTB
=10V.
V
IH
Logic input high threshold for PDN, RST, &
FIN inputs.
Logic input high threshold for PDN, RST, &
FIN inputs.
Logic input bias current for PDN, RST, &
FIN inputs.
0.7*VDD
V
V
IL
.3*VDD
V
I
LIN
-10
10
uA
For logic inputs, PDN, RST, & FIN
held at:-0.5V<V
LIN
<VDD
t
PDN
IXLD02 power down delay, V
PDN
logical low
to high transition.
IXLD02 power up delay, V
PDN
logical high to
low transition.
IXLD02 reset logic delay, V
RST
logical low to
high transition.
IXLD02 reset logic delay, V
RST
logical low to
high transition.
IXLD02 pulse frequency input, V
FIN,
logical
low to high transition to I
OUT
pulse delay.
f
FINmax
Maximum pulse frequency, FIN, logic input.
50
ns
30
ns
t
RST
100
ns
100
ns
t
FIN
50
ns
I
IBI
=400uA, I
IPW
=300uA, I
IOP
=1mA..
17
MHz I
IBI
=400uA, I
IPW
=300uA, I
IOP
=1mA..
I
OUT
Peak true pulse current output.
1.6
2
2.4
Amps I
IBI
=400uA, I
IPW
=300uA, I
IOP
=1mA.,
V
OUT
=V
OUTB
=10V.
ps
ps
t
R
t
F
Rise time
Fall time
600
600
T
ONDLY
On-time propagation delay
T
OFFDLY
Off-time propagation delay
P
Wmax
Pulse width maximum
T
j
Jitter
30
30
>1
<300
ns
ns
us
ps
V
OUT
OUT terminal voltage
8
12
V
I
IBI
=400uA, I
IPW
=300uA, I
IOP
=1mA,
1.4A<I
OUT
<2.6A peak.
Amps I
IBI
=400uA, I
IPW
=300uA, I
IOP
=1mA.,
V
OUT
=V
OUTB
=10V.
V
I
IBI
=400uA, I
IPW
=300uA, I
IOP
=1mA,
0A<I
OUT
<0.6A minimum.
I
OUTB
Minimum complement pulse current output.
0
0.2
0.4
V
OUTB
OUTB terminal voltage
8
12
Recommended Operating Conditions
Unless otherwise noted, VDD=VDDA=5V, T
C
=25C
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