- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224103 > K4F640411C-TC500 16M X 4 FAST PAGE DRAM, 50 ns, PDSO32 PDF資料下載
參數(shù)資料
| 型號： | K4F640411C-TC500 |
| 元件分類： | DRAM |
| 英文描述： | 16M X 4 FAST PAGE DRAM, 50 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-32 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 367K |
| 代理商： | K4F640411C-TC500 |
CMOS DRAM
K4F660411C, K4F640411C
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL load and 100pF.
Operation within the
tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If
tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that
tRCD
≥tRCD(max).
tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh
or Vol.
tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical char-
acteristics only. If
tWCS
≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
tCWD
≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the
tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
In test mode read cycle, the value of
tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
If
tRASS
≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
1.
2.
3.
4.
15.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4F640412C-JC450 | 16M X 4 FAST PAGE DRAM, 45 ns, PDSO32 |
| K4T1G044QC-ZCLE6 | 256M X 4 DDR DRAM, 0.45 ns, PBGA60 |
| K4T56163QI-ZLD50 | 16M X 16 SYNCHRONOUS DRAM, 0.5 ns, PBGA84 |
| K5A3240YT | Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM |
| K6R1004C1C | 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4F640411D-JC60 | 制造商:Samsung Semiconductor 功能描述: 制造商:Samsung Electro-Mechanics 功能描述:16M X 4 FAST PAGE DRAM, 60 ns, PDSO32 |
| K4F640412D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 4bit CMOS Dynamic RAM with Fast Page Mode |
| K4F640811B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8bit CMOS Dynamic RAM with Fast Page Mode |
| K4F640812D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8bit CMOS Dynamic RAM with Fast Page Mode |
| K4F641612B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 16bit CMOS Dynamic RAM with Fast Page Mode |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。