參數(shù)資料
型號(hào)： K4R271669F
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 128Mbit RDRAM(F-die)
中文描述： 128Mbit的RDRAM（架F -模）
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 292K
代理商： K4R271669F
Page 5
K4R271669F
Direct RDRAM
Version 1.41 Jan. 2004
General Description
Figure 2 is a block diagram of the 128Mbit RDRAM device.
It consists of two major blocks: a
“
core
”
block built from
banks and sense amps similar to those found in other types
of DRAM and a Direct Rambus
TM
interface block which
permits an external controller to access this core at up to
1.6GB/s.
Control Registers:
The CMD, SCK, SIO0 and SIO1
pins appear in the upper center of Figure 2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The nine bit REFR value is used for tracking the last
refreshed row. Most importantly, the five bit DEVID speci-
fies the device address of the RDRAM device on the
Channel.
Clocking:
The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
DQA,DQB Pins:
These 16 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multi-
plexed from/to two 64-bit data paths (running at one-eighth
the data frequency) inside the RDRAM device.
Banks:
The 16Mbyte core of the RDRAM device is
divided into thirty two 0.5Mbyte banks, each organized as
512 rows, with each row containing 64 dualocts, and each
dualoct containing 16 bytes. A dualoct is the smallest unit of
data that can be addressed.
Sense Amps:
The RDRAM device contains 34 sense
amps. Each sense amp consists of 512 bytes of fast storage
(256 for DQA and 256 for DQB) and can hold one-half of
one row of one bank of the RDRAM device. The sense amp
may hold any of the 512 half-rows of an associated bank.
However, each sense amp is shared between two adjacent
banks of the RDRAM device(except for sense amps 0, 15,
16 and 31). This introduces the restriction that adjacent
banks may not be simultaneously accessed.
RQ Pins:
These pins carry control and address informa-
tion. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
ROW Pins:
The principle use of these three pins is to
manage the transfer of data between the banks and the sense
amps of the RDRAM device. These pins are de-multiplexed
into a 24-bit ROWA (row-activate) or ROWR (row-opera-
tion) packet.
COL Pins:
The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM device. These pins are de-
multiplexed into a 23-bit COLC (column-operation) packet
and either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
ACT Command:
An ACT (activate) command from an
ROWA packet causes one of the 512 rows of the selected
bank to be loaded to its associated sense amps (two 256 byte
sense amps for DQA and two for DQB).
PRER Command:
A PRER (precharge) command from
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be acti-
vated.
RD Command:
The RD (read) command causes one of
the 64 dualocts of one of the sense amps to be transmitted on
the DQA/DQB pins of the Channel.
WR Command:
The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 64 dualocts of one of the sense amps during a subse-
quent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turn-
around.
PREC Precharge:
The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except that a
precharge operation is performed at the end of the column
operation. These commands provide a second mechanism
for performing precharge.
PREX Precharge:
After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
相關(guān)PDF資料
PDF描述
K4S160822D 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL
K4S161622D 512K x 16Bit x 2 Banks Synchronous DRAM
K4S161622E 1M x 16 SDRAM
K4S161622E-TC10 1M x 16 SDRAM
K4S161622E-TC55 1M x 16 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4R271669F-RCS8000 制造商:Samsung 功能描述:128 DIRECT RDRAM X16 WBGA - Trays
K4R271669F-TCS8000 制造商:Samsung 功能描述:128 DIRECT RDRAM X16 WBGA - Trays
K4R271669H-DCS8000 制造商:Samsung Semiconductor 功能描述:128MRDRAMDIRECT RDRAMX16FBGA - Bulk
K4R271669H-DCS8T00 制造商:Samsung Semiconductor 功能描述:128MRDRAMDIRECT RDRAMX16FBGA - Tape and Reel
K4R441869A 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*