參數(shù)資料
型號: K4S160822D
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL
中文描述: 2Mx8 SDRAM的1M × 8位× 2銀行同步DRAM LVTTL
文件頁數(shù): 6/46頁
文件大?。?/td> 1183K
代理商: K4S160822D
K4S160822D
CMOS SDRAM
- 6 -
Rev. 1.0 (Oct. 1999)
1. Unless otherwise notes, Input level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
) in LVTTL.
2. Measured with outputs open.
3. Refresh period is 32ms.
4. K4S160822DT-G**
5. K4S160822DT-F**
Notes :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit
Note
-7
-8
-H
-L
-10
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
t
RC
(min)
I
o
= 0 mA
100
90
85
85
75
mA
1
Precharge standby current in
power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 15ns
2
mA
I
CC2
PS
CKE & CLK
V
IL
(max), t
CC
=
2
Precharge standby current in
non power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
15
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
5
Active standby current in
power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 15ns
3
mA
I
CC3
PS
CKE & CLK
V
IL
(max), t
CC
=
3
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
25
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
15
mA
Operating current
(Burst mode)
I
CC4
I
o
= 0 mA
Page burst
2Banks activated
t
CCD
= 2CLKs
3
120
110
95
95
95
mA
1
2
95
85
95
85
85
Refresh current
I
CC5
t
RC
t
RC
(min)
90
80
mA
2
Self refresh current
I
CC6
CKE
0.2V
1
mA
3
250
uA
4
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