參數(shù)資料
型號: K6R4016C1C-I12
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256Kx16 Bit High Speed Static RAM(5V Operating).
中文描述: 256Kx16位高速靜態(tài)RAM(5V的工作)。
文件頁數(shù): 5/11頁
文件大小: 184K
代理商: K6R4016C1C-I12
K6R4016C1C-C, K6R4016C1C-E, K6R4016C1C-I
CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 5 -
September 2001
TEST CONDITIONS*
* The above test conditions are also applied at extended and industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
°
C, V
CC
=5.0V
±
10%, unless otherwise noted.)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
D
OUT
5pF*
480
255
+5.0V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
READ CYCLE*
* The above parameters are also guaranteed at extended and industrial temperature range.
Parameter
Symbol
K6R4016C1C-10
K6R4016C1C-12
K6R4016C1C-15
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
10
-
12
-
15
-
ns
Address Access Time
t
AA
-
10
-
12
-
15
ns
Chip Select to Output
t
CO
-
10
-
12
-
15
ns
Output Enable to Valid Output
t
OE
-
5
-
6
-
7
ns
UB, LB Access Time
t
BA
-
5
-
6
-
7
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
0
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
5
0
6
0
7
ns
Output Disable to High-Z Output
t
OHZ
0
5
0
6
0
7
ns
UB, LB Disable to High-Z Output
t
BHZ
0
5
0
6
0
7
ns
Output Hold from Address Change
t
OH
3
-
3
-
3
-
ns
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