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參數(shù)資料
| 型號： | K7A323600M-QC25 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | DRAM |
| 英文描述： | 1Mx36 & 2Mx18 Synchronous SRAM |
| 中文描述： | 1Mx36 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 247K |
| 代理商： | K7A323600M-QC25 |
1Mx36 & 2Mx18 Synchronous SRAM
- 16 -
Rev 2.0
Nov. 2003
K7A321800M
K7A323600M
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
Data
Address
CLK
ADS
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
512Kx36
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
512Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:19]
A
[19]
A
[0:18]
A
[19]
A
[0:18]
I/O
[0:71]
Microprocessor
Clock
ADSP
ADDRESS
[0:n]
Data Out
(Bank 0)
Bank 0 is selected by
CS
2
, and Bank 1 deselected by
CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
(Bank 1)
t
SS
t
SH
A1
A2
WRITE
CS
1
A
n+1
ADV
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by
CS
2
, and Bank 1 selected by
CS
2
t
CSS
t
CSH
CD
t
LZC
Q2-1
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
Don
′
t Care
Undefined
(ADSP CONTROLLED , ADSC=HIGH)
*Notes :
n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
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