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參數(shù)資料
| 型號(hào)： | K7N401801B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Flash - NOR IC; NOR Flash Type:Page Mode Access; Memory Size:256MB; Memory Configuration:128K x 16; Access Time, Tacc:110ns; Page/Burst Read Access:25ns; Sector Type:Uniform; Package/Case:64-BGA; Supply Voltage Max:3.6V |
| 中文描述： | 128K × 36至 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 386K |
| 代理商： | K7N401801B |
128Kx36 & 256Kx18 Pipelined N
t
RAM
TM
- 6 -
Rev 2.0
Nov. 2003
K7N401801B
K7N403601B
FUNCTION DESCRIPTION
The K7N403601B and K7N401801B are N
t
RAM
TM
designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
N
t
RAM
TM
latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS
1
, CS
2
, CS
2
)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS
1
, CS
2
, CS
2
) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-
lined N
t
RAM
TM
uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO=High)
Note :
1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
LBO PIN
HIGH
Case 1
Case 2
Case 3
Case 4
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
0
1
1
A
0
1
0
1
0
A
1
1
1
0
0
A
0
0
1
0
1
A
1
1
1
0
0
A
0
1
0
1
0
First Address
Fourth Address
BQ TABLE
(Linear Burst, LBO=Low)
Note :
1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
LBO PIN
LOW
Case 1
Case 2
Case 3
Case 4
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
1
1
0
A
0
1
0
1
0
A
1
1
1
0
0
A
0
0
1
0
1
A
1
1
0
0
1
A
0
1
0
1
0
First Address
Fourth Address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7N401801B-QC13 | 256 Megabit, 3.0 Volt-only Page Mode Flash Memory |
| K7N403601B | 128Kx36 & 256Kx18 Pipelined NtRAM |
| K7N801849B-QC25 | THERMISTOR, NTC; Series:B572; Thermistor type:NTC; Resistance:10R; Tolerance, resistance:20%; Beta value:2900; Temperature, lower limit, beta value:25(degree C); Temperature, upper limit, beta value:100(degree C); Case RoHS Compliant: Yes |
| K7N801801B | 256Kx36 & 512Kx18-Bit Pipelined NtRAM |
| K7N803601B | 256Kx36 & 512Kx18-Bit Pipelined NtRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7N401801B-QC13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Pipelined NtRAM |
| K7N401801B-QC13000 | 制造商:Samsung Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 4M-Bit 256K x 18 4.2ns 100-Pin TQFP Tray |
| K7N401801B-QI13 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Pipelined NtRAM |
| K7N401801M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Pipelined NtRAM-TM |
| K7N401801M-QC1500 | 制造商:Samsung SDI 功能描述: |
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