參數(shù)資料
型號: K7Q161854A-FC20
元件分類: SRAM
英文描述: 1M X 18 QDR SRAM, 2.2 ns, PBGA165
封裝: 13 X 15 MM, FBGA-165
文件頁數(shù): 16/17頁
文件大?。?/td> 510K
代理商: K7Q161854A-FC20
512Kx36 & 1Mx18 QDRTM b4 SRAM
- 8 -
Rev 1.0
July. 2002
K7Q163654A
K7Q161854A
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Notes: 1. X means "Don
′t Care".
2. The rising edge of clock is symbolized by (
↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
K
R
W
D
Q
OPERATION
D(A1)
D(A2)
D(A3)
D(A4)
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Stopped
X
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Previous
state
Clock Stop
H
X
High-Z
No Operation
L
X
DOUT
at C(t+1)
DOUT
at C(t+1)
DOUT
at C(t+2)
DOUT
at C(t+2)
Read
H
L
Din
at K(t+1)
Din
at K(t+1)
Din
at K(t+2)
Din
at K(t+2)
X
Write
WRITE TRUTH TABLE(x18)
Notes: 1. X means "Don
′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(
↑ ).
K
W
BW0
BW1
OPERATION
H
X
READ/NOP
H
X
READ/NOP
L
WRITE ALL BYTEs ( K
↑ )
L
WRITE ALL BYTEs ( K
↑ )
L
H
WRITE BYTE 0 ( K
↑ )
L
H
WRITE BYTE 0 ( K
↑ )
L
H
L
WRITE BYTE 1 ( K
↑ )
L
H
L
WRITE BYTE 1 ( K
↑ )
L
H
WRITE NOTHING ( K
↑ )
L
H
WRITE NOTHING ( K
↑ )
WRITE TRUTH TABLE(x36)
Notes: 1. X means "Don
′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(
↑ ).
K
W
BW0
BW1
BW2
BW3
OPERATION
H
X
READ/NOP
H
X
READ/NOP
L
WRITE ALL BYTEs ( K
↑ )
L
WRITE ALL BYTEs ( K
↑ )
L
H
WRITE BYTE 0 ( K
↑ )
L
H
WRITE BYTE 0 ( K
↑ )
L
H
L
H
WRITE BYTE 1 ( K
↑ )
L
H
L
H
WRITE BYTE 1 ( K
↑ )
L
H
L
WRITE BYTE 2 and BYTE 3 ( K
↑ )
L
H
L
WRITE BYTE 2 and BYTE 3 ( K
↑ )
L
H
WRITE NOTHING ( K
↑ )
L
H
WRITE NOTHING ( K
↑ )
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