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參數(shù)資料
| 型號： | K7Q161854A-FC20 |
| 元件分類： | SRAM |
| 英文描述： | 1M X 18 QDR SRAM, 2.2 ns, PBGA165 |
| 封裝： | 13 X 15 MM, FBGA-165 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 510K |
| 代理商： | K7Q161854A-FC20 |
512Kx36 & 1Mx18 QDRTM b4 SRAM
- 10 -
Rev 1.0
July. 2002
K7Q163654A
K7Q161854A
AC TIMING CHARACTERISTICS(VDD=2.5V
±0.1V, TA=0°C to +70°C)
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W,BW0,BW1 and (BW2, BW3, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0
°C, 2.6V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 2.4V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
PARAMETER
SYMBOL
-20
-16
-13
-10
UNITS NOTES
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock
Clock Cycle Time(K, K, C, C)
tKHKH
5
6
7.5
10
ns
Clock HIGH time (K, K, C, C)
tKHKL
2.0
2.4
3.0
3.5
ns
Clock LOW time (K, K, C, C)
tKLKH
2.0
2.4
3.0
3.5
ns
Clock to clock (K
↑ → K↑, C↑ → C↑)
tKHKH
2.2
2.75
2.7
3.3
3.4
4.1
4.6
5.4
ns
Clock to data clock (K
↑ → C↑, K↑→ C↑)
tKHCH
0.0
1.7
0.0
2.0
0.0
2.5
0.0
3.0
ns
Output Times
C, C High to Output Valid
tCHQV
2.2
2.5
3.0
ns
3
C, C High to Output hold
tCHQX
1.0
1.2
ns
3
C High to Output High-Z
tCHQZ
2.2
2.5
3.0
ns
3
C High to Output Low-Z
tCHQX1
1.0
1.2
ns
3
Setup Times
Address valid to K rising edge
tAVKH
0.6
0.7
0.8
1.0
ns
Control inputs valid to K rising edge
tIVKH
0.6
0.7
0.8
1.0
ns
2
Data-in valid to K, K rising edge
tDVKH
0.6
0.7
0.8
1.0
ns
Hold Times
K rising edge to address hold
tKHAX
0.6
0.7
0.8
1.0
v
K rising edge to control inputs hold
tKHIX
0.6
0.7
0.8
1.0
ns
K, K rising edge to data-in hold
tKHDX
0.6
0.7
0.8
1.0
ns
VDDQ
VIL
VDDQ+0.7V
20% tKHKH(MIN)
VSS
VIH
VSS-0.7V
20% tKHKH(MIN)
Undershoot Timing
Overershoot Timing
Note: For power-up, VIH
≤ VDDQ+0.3V and VDD ≤ 2.4V and VDDQ ≤ 1.4V for t ≤ 200ms
OPERATING CONDITIONS (0
°C ≤ TA ≤ 70°C)
PARAMETER
SYMBOL
MIN
MAX
UNIT
Supply Voltage
VDD
2.4
2.6
V
VDDQ
1.4
1.9
V
Reference Voltage
VREF
0.68
0.95
V
Ground
VSS
0
V
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