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參數(shù)資料
| 型號： | K9F6408U0C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8M x 8 Bit NAND Flash Memory |
| 中文描述： | 8米× 8位NAND閃存 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 784K |
| 代理商： | K9F6408U0C |
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FLASH MEMORY
7
K9F6408U0C
PIN DESCRIPTION
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
Pin Name
Pin Function
I/O
0
~ I/O
7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation .
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
Vcc
Q
OUTPUT BUFFER POWER
Vcc
Q
is the power supply for Output Buffer.
Vcc
Q
is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
V
CC
is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
GND
GND INPUT FOR ENABLING SPARE AREA
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state .
DNU
DO NOT USE
Leave it disconnected.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K9F6408U0C-B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit Bit NAND Flash Memory |
| K9F6408U0C-F | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit NAND Flash Memory |
| K9F6408U0C-H | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit Bit NAND Flash Memory |
| K9F6408U0C-Q | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit NAND Flash Memory |
| K9F6408U0C-T | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8 Bit Bit NAND Flash Memory |
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