參數(shù)資料
型號： K9K2G08Q0M-PIB0
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
中文描述： 256M × 8位/ 128M的× 16位NAND閃存
文件頁數(shù)： 34/38頁
文件大?。?/td> 734K
代理商： K9K2G08Q0M-PIB0
FLASH MEMORY
34
K9K2G08Q0M-YCB0,YIB0,PCB0,PIB0
K9K2G08U0M-YCB0,YIB0,PCB0,PIB0
K9K2G16Q0M-YCB0,YIB0,PCB0,PIB0
K9K2G16U0M-YCB0,YIB0,PCB0,PIB0
K9K2G08U0M-VCB0,VIB0,FCB0,FIB0
Figure 13. Block Erase Operation
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A
18
to A
28
(X8) or A
17
to A
27
(X16) is valid while A
12
to A
17
(X8) or A
11
to A
16
(X16) is ignored. The Erase
Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
60h
Block Add. : A
12
~ A
28
(X8)
or A
11
~ A
27
(X16)
R/B
Address Input(3Cycle)
I/O
0
Pass
D0h
70h
Fail
t
BERS
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table2. Read Staus Register Definition
NOTE
:
1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
I/O No.
Page Program
Block Erase
Cache Prorgam
Read
Definition
I/O 0
Pass/Fail
Pass/Fail
Pass/Fail(N)
Not use
Pass : "0" Fail : "1"
I/O 1
Not use
Not use
Pass/Fail(N-1)
Not use
Pass : "0" Fail : "1"
I/O 2
Not use
Not use
Not use
Not use
Don’t -cared
I/O 3
Not Use
Not Use
Not Use
Not Use
Don’t -cared
I/O 4
Not Use
Not Use
Not Use
Not Use
Don’t -cared
I/O 5
Ready/Busy
Ready/Busy
True Ready/Busy
Ready/Busy
Busy : "0" Ready : "1"
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Busy : "0" Ready : "1"
I/O 7
Write Protect
Write Protect
Write Protect
Write Protect
Protected : "0" Not Protected
I/O 8~15
(X16 device
only)
Not use
Not use
Not use
Not use
Don’t -care
I/Ox
"0"
"1"
相關(guān)PDF資料
PDF描述
K9K2G16Q0M-PIB0 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G08Q0M-Y 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G08Q0M-YIB0 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G08U0M-FCB0 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G08U0M-FIB0 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K9K2G08Q0M-Y 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G08Q0M-YCB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G08Q0M-YIB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G08R0A 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY
K9K2G08R0A-JIB0000 制造商:Samsung 功能描述:2GB SLC DIE STACK X8 FBGA - Trays
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