參數(shù)資料
型號(hào)： K9W4G16U1M
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
中文描述： 256M × 8位/ 128M的× 16位NAND閃存
文件頁(yè)數(shù)： 13/40頁(yè)
文件大小： 641K
代理商： K9W4G16U1M
FLASH MEMORY
13
K9W4G08U1M
K9K2G08U0M
K9W4G16U1M
K9K2G16Q0M
K9K2G16U0M
K9K2G08Q0M
CAPACITANCE
(
T
A
=25
°
C, V
CC
=1.8V/3.3V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Max
Unit
K9K2GXXX0M
K9W4GXXU1M
Input/Output Capacitance
C
I/O
V
IL
=0V
20
40
pF
Input Capacitance
C
IN
V
IN
=0V
20
40
pF
VALID BLOCK
NOTE
:
1. The
device
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
. Do not erase or pro-
gram factory-marked bad blocks.
Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
* :
Each K9K2GXXX0M chip in the K9W4GXXU1M has Maximum 40 invalid blocks.
Parameter
Symbol
Min
Max
Unit
K9K2GXXX0M
Valid Block Number
N
VB
2008
2048
Blocks
K9W4GXXU1M
Valid Block Number
N
VB
4016*
4096*
Blocks
AC TEST CONDITION
(K9XXGXXXXM-XCB0 :TA=0 to 70
°
C, K9XXGXXXXM-XIB0:TA=-40 to 85
°
C
K9K2GXXQ0M : Vcc=1.70V~1.95V , K9XXGXXUXM : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9K2GXXQ0M
K9XXGXXUXM
Input Pulse Levels
0V to Vcc
0.4V to 2.4V
Input Rise and Fall Times
5ns
5ns
Input and Output Timing Levels
Vcc/2
1.5V
K9K2GXXQ0M:Output Load (Vcc:1.8V +/-10%)
K9XXGXXUXM:Output Load (Vcc:3.0V +/-10%)
1 TTL GATE and CL=30pF
1 TTL GATE and CL=50pF
K9XXGXXUXM:Output Load (Vcc:3.3V +/-10%)
-
1 TTL GATE and CL=100pF
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
PRE
Mode
H
L
L
H
X
X
Read Mode Command Input
Address Input(5clock)
L
H
L
H
X
X
H
L
L
H
H
X
Write Mode Command Input
Address Input(5clock)
L
H
L
H
H
X
L
L
L
H
H
X
Data Input
L
L
L
H
X
X
Data Output
X
X
X
X
H
X
X
During Read(Busy)
X
X
X
X
X
H
X
During Program(Busy)
X
X
X
X
X
H
X
During Erase(Busy)
X
X
(1)
X
X
X
L
X
Write Protect
X
X
H
X
X
0V/V
CC
(2)
0V/V
CC
(2)
Stand-by
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