28 FN7693.2 May 2, 2011 ADC Evaluation Platform Intersil offers an ADC Evaluation platform which can be used to evaluate any of the KA" />
參數(shù)資料
型號(hào)： KAD5510P-25Q48
廠商： Intersil
文件頁(yè)數(shù)： 21/31頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT CMOS 250MSPS 48QFN
標(biāo)準(zhǔn)包裝： 40
系列： FemtoCharge™
位數(shù)： 10
采樣率（每秒）： 250M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 254mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN（7x7）
包裝： 托盤
輸入數(shù)目和類型： *
KAD5510P
28
FN7693.2
May 2, 2011
ADC Evaluation Platform
Intersil offers an ADC Evaluation platform which can be used to
evaluate any of the KADxxxxx ADC family. The platform consists
of a FPGA based data capture motherboard and a family of ADC
daughtercards. This USB based platform allows a user to quickly
evaluate the ADC’s performance at a user’s specific application
frequency requirements. More information is available at:
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
PCB Layout Example
For an example application circuit and PCB layout, please refer to
the evaluation board documentation provided in the web product
folder at:
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and terminations
as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
LVDS Outputs
Output traces and connections must be designed for 50
Ω (100Ω
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50
Ω
characteristic impedance. Care should be taken when using the
DDR CMOS outputs at clock rates greater than 200MHz. Series
termination resistors close to the ADC should drive short traces
with minimum parasitic loading to assure adequate signal
integrity
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO) which will not
be operated do not require connection to ensure optimal ADC
performance. These inputs can be left floating if they are not
used. The SDO output must be connected to OVDD with a 4.7k
resistor or the ADC will not exit the reset state. Tri-level inputs
(NAPSLP) accept a floating input as a valid state, and therefore
should be biased according to the desired functionality.
General PowerPAD Design
Considerations
Figure 49 is a generic illustration of how to use vias to remove
heat from a QFN package with an exposed thermal pad. A
specific example can be found in the evaluation board PCB
layout previously referenced.
FIGURE 48. VCM_OUT OUTPUT
Equivalent Circuits (Continued)
VCM
AVDD
0.535V
+
–
FIGURE 49. PCB VIA PATTERN
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KAD5510P-50Q72 功能描述:IC ADC 10BIT 500MSPS SGL 72-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:FemtoCharge™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個(gè)單端，單極
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