19 FN6807.4 October 1, 2010 User-Initiated Reset Recalibration of the ADC can be initiated at any time by driving the RESETN pin low f" />
參數(shù)資料
型號: KAD5512P-17Q72
廠商: Intersil
文件頁數(shù): 11/36頁
文件大小: 0K
描述: IC ADC 12BIT 170MSPS SGL 72-QFN
產(chǎn)品培訓模塊: High-Speed Analog-to-Digital Converters
標準包裝: 1
系列: FemtoCharge™
位數(shù): 12
采樣率(每秒): 170M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 253mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應商設備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
KAD5512P
19
FN6807.4
October 1, 2010
User-Initiated Reset
Recalibration of the ADC can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with less than 0.5mA
open-state leakage is recommended so the internal high
impedance pull-up to OVDD can assure exit from the reset
state. As is the case during power-on reset, the SDO,
RESETN and DNC pins must be in the proper state for the
calibration to successfully execute.
The performance of the KAD5512P changes with
variations in temperature, supply voltage or sample rate.
The extent of these changes may necessitate
recalibration, depending on system performance
requirements. Best performance will be achieved by
recalibrating the ADC under the environmental conditions
at which it will operate.
A supply voltage variation of less than 100mV will
generally result in an SNR change of less than 0.5dBFS
and SFDR change of less than 3dBc.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less than
75MSPS will typically result in an SNR change of less than
0.5dBFS and an SFDR change of less than 3dBc.
Figures 25 and 26 show the effect of temperature on
SNR and SFDR performance with calibration performed
at -40°C, +25°C, and +85°C. Each plot shows the
variation of SNR/SFDR across temperature after a single
calibration at -40°C, +25°C and +85°C. Best
performance is typically achieved by a user-initiated
calibration at the operating conditions, as stated earlier.
However, it can be seen that performance drift with
temperature is not a very strong function of the
temperature at which the calibration is performed. Full-
rated performance will be achieved after power-up
calibration regardless of the operating conditions.
Analog Input
The ADC core contains a fully differential input
(VINP/VINN) to the sample and hold amplifier (SHA). The
ideal full-scale input voltage is 1.45V, centered at the
VCM voltage of 0.535V as shown in Figure 27.
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as
shown in Figures 28 through 30. An RF transformer will
give the best noise and distortion performance for
wideband and/or high intermediate frequency (IF)
inputs. Two different transformer input schemes are
shown in Figures 28 and 29.
FIGURE 24. CALIBRATION TIMING
CLKP
CLKN
CLKOUTP
RESETN
ORP
CALIBRATION
BEGINS
CALIBRATION
COMPLETE
CALIBRATION
TIME
FIGURE 25. SNR PERFORMANCE vs TEMPERATURE
-4
-3
-2
-1
0
1
2
3
-40
-15
10
35
60
85
S
NR
C
HANGE
(dB
fs
)
CAL DONE AT
+85°C
TEMPERATURE (°C)
CAL DONE AT
-40°C
CAL DONE AT
+25°C
FIGURE 26. SFDR PERFORMANCE vs TEMPERATURE
-15
-10
-5
0
5
10
15
-40
-15
10
35
60
85
SFD
R
CHA
NGE
(
d
Bc
)
TEMPERATURE (°C)
CAL DONE AT
-40°C
CAL DONE AT
+25°C
CAL DONE AT
+85°C
FIGURE 27. ANALOG INPUT RANGE
1.0
1.8
0.6
0.2
1.4
INP
INN
VCM
0.535V
0.725V
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