29 FN6807.4 October 1, 2010 Dev ice T e st C0 test_io User Test Mode [1:0] 00 = Single 01 = Alternate 10 = Reserved 11 = Reserved Outp" />
參數(shù)資料
型號: KAD5512P-17Q72
廠商: Intersil
文件頁數(shù): 22/36頁
文件大小: 0K
描述: IC ADC 12BIT 170MSPS SGL 72-QFN
產(chǎn)品培訓(xùn)模塊: High-Speed Analog-to-Digital Converters
標準包裝: 1
系列: FemtoCharge™
位數(shù): 12
采樣率(每秒): 170M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 253mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
KAD5512P
29
FN6807.4
October 1, 2010
Dev
ice
T
e
st
C0
test_io
User Test Mode
[1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
Output Test Mode [3:0]
00h
G
0 = Off
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checker Board
5 = Reserved
6 = Reserved
7 = One/Zero
Word
Toggle
8 = User Input
9-15 = Reserved
C1
Reserved
00h
G
C2
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C3
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C4
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C5
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C6-FF
Reserved
NOTE:
15. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal
pull-up.
TABLE 17. SPI MEMORY MAP (Continued)
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
(LSB)
Def.
Value
(Hex)
Indexed/
Global
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