35 FN6807.4 October 1, 2010 Package Outline Drawing L48.7x7E 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 2/09 located within the " />
參數(shù)資料
型號: KAD5512P-17Q72
廠商: Intersil
文件頁數(shù): 29/36頁
文件大小: 0K
描述: IC ADC 12BIT 170MSPS SGL 72-QFN
產(chǎn)品培訓(xùn)模塊: High-Speed Analog-to-Digital Converters
標(biāo)準(zhǔn)包裝: 1
系列: FemtoCharge™
位數(shù): 12
采樣率(每秒): 170M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 253mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
KAD5512P
35
FN6807.4
October 1, 2010
Package Outline Drawing
L48.7x7E
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 2/09
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance: Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSEY14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.
1.
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
C
0. 2 REF
0. 05 MAX.
0. 00 MIN.
5
B
6
PIN 1
INDEX AREA
1
24
13
0.10
A
MC
B
4
A
4X 5.50
48X 0.40
48X 0.25
44X 0.50
7.00
0.90 Max
48X 0.25
48X 0.60
44X 0.50
5.60 Sq
6.80 Sq
6
PIN 1
INDEX AREA
Exp. DAP
5.60 Sq.
SEE DETAIL "X"
SEATING PLANE
0.08
0.10
C
(4X)
0.15
12
25
48
37
36
TOP VIEW
BOTTOM VIEW
Connect Exp. DAP (PAD) to AVSS with multiple vias to a low
thermal impedance plane
7.
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