- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2002 > KAD5514P-12Q72 (Intersil)IC ADC 14BIT 125MSPS SGL 72-QFN PDF資料下載
參數(shù)資料
| 型號： | KAD5514P-12Q72 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 16/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 125MSPS SGL 72-QFN |
| 產(chǎn)品培訓(xùn)模塊： | High-Speed Analog-to-Digital Converters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 376mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
23
FN6804.2
September 10, 2009
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the
data transfer. By default, all data is presented on the serial
data input/output (SDIO) pin in three-wire mode. The state of
the SDIO pin is set automatically in the communication
protocol (described in the following). A dedicated serial data
output pin (SDO) can be activated by setting 0x00[7] high to
allow operation in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5514P functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an
unaddressed device is asserted in four-wire mode.
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in three-wire mode). If
multiple slave devices are selected for reading at the same
time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command,
SCLK must be static low before the CSB transition. Data can
be presented in MSB-first order or LSB-first order. The
default is MSB-first, but this can be changed by setting
ordering for the MSB-first and LSB-first modes, respectively.
In MSB-first mode the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
In the default mode the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits,
W1 and W0, determine the number of data bytes to be read
or written (see Table 6). The lower 13 bits contain the first
address for the data transfer. This relationship is illustrated in
Figure 37, and timing values are given in the “Switching
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from
the ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active.
Stalling of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or
more, CSB is allowed stall in the middle of the
instruction/address bytes or before the first data byte. If CSB
transitions to a high state after that point the state machine
will reset and terminate the data transfer.
TABLE 6. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
FIGURE 37. WRITE TIMING
tS
tHI
tCLK
tLO
R/W
W1
W0
A12 A11 A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
tH
tDHW
tDSW
SPI WRITE
CSB
SCLK
SDIO
FIGURE 38. READ TIMING
(3 WIRE MODE)
(4 WIRE MODE)
R/W W1 W0 A12 A11 A10 A9
A2 A1
D7 D6
D3 D2
D1
D7
D3
D2
D1 D0
A0
WRITING A READ COMMAND
READING DATA
D0
tH
tDHR
tDVR
SPI READ
tHI
tCLK
tLO
tDHW
tDSW
tS
CSB
SCLK
SDIO
SDO
KAD5514P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KAD5610P-25Q72 | IC ADC 10BIT 250MSPS DUAL 72-QFN |
| KAD5612P-17Q72 | IC ADC 12BIT 170MSPS DUAL 72-QFN |
| LA72715NV-TLM-E | IC AUDIO DECODER JPN MTS 24SSOP |
| LICAL-DEC-LS001 | IC DECODER LOW SECURITY 8DIP |
| LICAL-DEC-MS001 | IC DECODER MS SERIES 20-SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KAD5514P-17Q48 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:14-Bit, 250/210/170/125MSPS ADC |
| KAD5514P-17Q72 | 制造商:Intersil Corporation 功能描述:14-BIT, 170MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 170MSPS SGL 72-QFN |
| KAD5514P-21Q48 | 制造商:Intersil Corporation 功能描述:14-BIT, 210MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 210MSPS SGL 48-QFN |
| KAD5514P-21Q72 | 制造商:Intersil Corporation 功能描述:14-BIT, 210MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 210MSPS SGL 72-QFN |
| KAD5514P-25Q48 | 制造商:Intersil Corporation 功能描述:14-BIT, 250MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 250MSPS SGL 48-QFN 制造商:Intersil Corporation 功能描述:IC, ADC, 14BIT, Resolution (Bits):14bit, Sampling Rate:250MSPS, Supply Voltage T 制造商:Intersil Corporation 功能描述:IC, ADC, 14BIT, Resolution (Bits):14bit, Sampling Rate:250MSPS, Supply Voltage Type:Single, Supply Voltage Min:1.7V, Supply Voltage Max:1.9V, Supply Current:170mA, Digital IC Case Style:QFN, No. of Pins:48, Data Interface:SPI, MSL:- , RoHS Compliant: Yes |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。