參數(shù)資料
型號: KAD5514P-12Q72
廠商: Intersil
文件頁數(shù): 20/34頁
文件大小: 0K
描述: IC ADC 14BIT 125MSPS SGL 72-QFN
產(chǎn)品培訓模塊: High-Speed Analog-to-Digital Converters
標準包裝: 1
系列: FemtoCharge™
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 376mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應商設備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
27
FN6804.2
September 10, 2009
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC2: USER_PATT2_LSB
ADDRESS 0XC3: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
SPI Memory Map
TABLE 15. OUTPUT TEST MODES
VALUE
0xC0[3:0]
WORD 1
WORD 2
OUTPUT TEST
MODE
0000
Off
0001
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
0110
Reserved
N/A
0111
One/Zero
0xFFFF
0x0000
1000
User Pattern
user_patt1
user_patt2
TABLE 16. SPI MEMORY MAP
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Def. Value
(Hex)
Indexed/
Global
SPI
Config
00
port_config
SDO
Active
LSB First
Soft
Reset
Mirror
(bit5)
Mirror
(bit6)
Mirror
(bit7)
00h
G
01
reserved
Reserved
02
burst_end
Burst end address [7:0]
00h
G
03-07
reserved
Reserved
Info
08
chip_id
Chip ID #
Read only
G
09
chip_version
Chip Version #
Read only
G
Ind
exed
Device
Co
nf
ig/Co
n
tr
ol
10
device_index_A
Reserved
ADC01
ADC00
00h
I
11-1F
reserved
Reserved
20
offset_coarse
Coarse Offset
cal. value
I
21
offset_fine
Fine Offset
cal. value
I
22
gain_coarse
Reserved
Coarse Gain
cal. value
I
23
gain_medium
Medium Gain
cal. value
I
24
gain_fine
Fine Gain
cal. value
I
25
modes
Reserved
Power-Down Mode [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
other codes = reserved
00h
NOT
affected by
Soft Reset
I
26-5F
reserved
Reserved
KAD5514P
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