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參數(shù)資料
型號(hào)： KAD5514P-12Q72
廠(chǎng)商： Intersil
文件頁(yè)數(shù)： 33/34頁(yè)
文件大小： 0K
描述： IC ADC 14BIT 125MSPS SGL 72-QFN
產(chǎn)品培訓(xùn)模塊： High-Speed Analog-to-Digital Converters
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 376mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，單極
8
FN6804.2
September 10, 2009
Switching Specifications
PARAMETER
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
ADC OUTPUT
Aperture Delay
tA
375
ps
RMS Aperture Jitter
jA
60
fs
Output Clock to Data
Propagation Delay, LVDS Mode
(Note 9)
DDR, Rising Edge
tDC
-260
-50
120
ps
DDR, Falling Edge
tDC
-160
10
230
ps
SDR, Falling Edge
tDC
-260
-40
230
ps
Output Clock to Data
Propagation Delay, CMOS Mode
(Note 9)
DDR, Rising Edge
tDC
-220
-10
200
ps
DDR, Falling Edge
tDC
-310
-90
110
ps
SDR, Falling Edge
tDC
-310
-50
200
ps
Latency (Pipeline Delay)
L
8.5
cycles
Overvoltage Recovery
tOVR
1cycles
SPI INTERFACE (Notes 10, 11)
SCLK Period
Write Operation
tCLK
16
cycles
(Note 10)
Read Operation
tCLK
66
cycles
SCLK Duty Cycle (tHI/tCLK or
tLO/tCLK)
Read or Write
25
50
75
%
CSB
↓ to SCLK↑ Setup Time
Read or Write
tS
1cycles
CSB
↑ after SCLK↑ Hold Time
Read or Write
tH
3cycles
Data Valid to SCLK
↑ Setup Time Write
tDSW
1cycles
Data Valid after SCLK
↑ Hold
Time
Write
tDHW
3cycles
Data Valid after SCLK
↓ Time
Read
tDVR
16.5
cycles
Data Invalid after SCLK
↑ Time
Read
tDHR
3cycles
Sleep Mode CSB
↓ to SCLK↑
Setup Time (Note 12)
Read or Write in Sleep Mode
tS
150
s
NOTES:
8. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
depending on desired function.
9. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
applications. Contact factory for more info if needed.
10. SPI Interface timing is directly proportional to the ADC sample period (4ns at 250Msps).
11. The SPI may operate asynchronously with respect to the ADC sample clock.
12. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup
time (4ns min).
KAD5514P
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KAD5514P-17Q48 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:14-Bit, 250/210/170/125MSPS ADC
KAD5514P-17Q72 制造商:Intersil Corporation 功能描述:14-BIT, 170MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 170MSPS SGL 72-QFN
KAD5514P-21Q48 制造商:Intersil Corporation 功能描述:14-BIT, 210MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 210MSPS SGL 48-QFN
KAD5514P-21Q72 制造商:Intersil Corporation 功能描述:14-BIT, 210MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 210MSPS SGL 72-QFN
KAD5514P-25Q48 制造商:Intersil Corporation 功能描述:14-BIT, 250MSPS SINGLE-CHANNEL ADC, PROGRAMMABLE LVDS/LVCMOS - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 14BIT 250MSPS SGL 48-QFN 制造商:Intersil Corporation 功能描述:IC, ADC, 14BIT, Resolution (Bits):14bit, Sampling Rate:250MSPS, Supply Voltage T 制造商:Intersil Corporation 功能描述:IC, ADC, 14BIT, Resolution (Bits):14bit, Sampling Rate:250MSPS, Supply Voltage Type:Single, Supply Voltage Min:1.7V, Supply Voltage Max:1.9V, Supply Current:170mA, Digital IC Case Style:QFN, No. of Pins:48, Data Interface:SPI, MSL:- , RoHS Compliant: Yes
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