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參數(shù)資料
| 型號： | KFW4G16Q2M-DED6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FLASH MEMORY(66MHz) |
| 中文描述： | 閃存（66MHz的） |
| 文件頁數(shù)： | 93/125頁 |
| 文件大?。?/td> | 1632K |
| 代理商： | KFW4G16Q2M-DED6 |
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OneNAND1G(KFG1G16Q2M-DEB6)
FLASH MEMORY
93
OneNAND2G(KFH2G16Q2M-DEB6)
OneNAND4G(KFW4G16Q2M-DEB6)
3.12 Dual Operations
The device has independent dual data buffers on-chip (except during the Boot Load period) that enables higher
performance read and program operation.
3.12.1 Read-While-Load Operation
This operation accelerates the read performance of the device by enabling data to be read out by the host from one DataRAM buffer
while the other DataRAM buffer is being loaded with data from the NAND Flash Array memory.
Page A
Page B
1) Data Load
2) Data Load
Data
Buffer1
Data
Buffer0
2) Data Read
3) Data Read
3) Data Load
The dual data buffer architecture provides the capability of executing a data-read operation from one of DataRAM buffers during a
simultaneous data-load operation from Flash to the other buffer. Simultaneous load and read operation to same data buffer is
prohibited. See sections 3.6 and 3.7 for more information on Load and Read Operations.
If host sets FBA, FSA, or FPA while loading into designated page, it will fail the internal load operation. Address registers should not
be updated until internal operation is completed.
3.12.2 Write-While-Program Operation
This operation accelerates the programming performance of the device by enabling data to be written by the host into one DataRAM
buffer while the NAND Flash Array memory is being programmed with data from the other DataRAM buffer.
The dual data buffer architecture provides the capability of executing a data-write operation to one of DataRAM buffers during simul-
taneous data-program operation to Flash from the other buffer. Simultaneous program and write operation to same data buffer is
prohibited. See sections 3.8 for more information on Program Operation.
If host sets FBA, FSA, or FPA while programming into designated page, it will fail the internal program operation. Address registers
should not be updated until internal operation is completed.
Page A
Page B
Data
Buffer1
Data
Buffer0
2) Data Write
2) Program
3) Program
1) Data Write
3) Data Write
相關PDF資料 |
PDF描述 |
|---|---|
| KFW4G16Q2M | FLASH MEMORY(66MHz) |
| KFG1G16Q2M-DEB | FLASH MEMORY |
| KFG1G16Q2M-DED | FLASH MEMORY |
| KFG1G16Q2M-DIB | FLASH MEMORY |
| KFG1G16Q2M-DID | FLASH MEMORY |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KFW4G16Q2M-DIB5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFW4G16Q2M-DIB6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFW4G16Q2M-DID5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFW4G16Q2M-DID6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
| KFW4G16U2M-DEB5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY(54MHz) |
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