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| 型號： | KM4232W259A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | CMOS Window RAM（1M Byte Dual Ported DRAM Array）(CMOS視窗RAM（1M字節(jié)的雙口動態(tài)RAM陣列）) |
| 中文描述： | 窗口的CMOS內(nèi)存（1M字節(jié)雙端口內(nèi)存陣列）（視窗的CMOS存儲器（100萬字節(jié)的雙口動態(tài)內(nèi)存陣列）） |
| 文件頁數(shù)： | 1/46頁 |
| 文件大小： | 836K |
| 代理商： | KM4232W259A |
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KM4232W259A
CMOS WINDOW RAM
Rev.0 (August 1997)
The KM4232W259A is a 1M Byte Dual Ported DRAM array
with added features that accelerate graphic operations in a GUI
environment. A 256-bit internal bus allows transferring up to 32
bytes of data on a single chip. All necessary features present to
support fully functional SCROLL and ALIGNED BLOCK-MOVE
graphic operations.
The 16-bit Serial Output port is comprised of two 128-byte serial
registers. This allows relaxed system timing and full CPU access
while the registers are being emptied to the display.
To enhance the block transfer performance for Windows-based
operations, the KM4232W259A also provides Block Write Mode
of 8-columns which allows 32-bytes maximum of block data
transfer at a time. A choice of 2-colors can be used in any com-
bination of foreground and background mixing.(e.g. For mono-
chrome and color text expansion) This operation is useful for
graphic Fill and Text operations.
A combination of Mixed Modes(see truth table) defined by the
CAS falling edge is also supported. This performance enhance-
ment feature allows system designers to change the mode of
operation on the fly within Ultra Fast Page cycle time.
1M Byte Frame-Buffer on a single chip
2.1 G Byte/Second Internal Bus :
-. Fast Window Drawing Operations
-. Fill at up to 2.1 G Byte/Second
-. Aligned BitBLT at up to 0.64 G Byte/Second
8-Column Block Write with Bit and Byte Masking Capability
267 M Bytes/Second CPU Read/Write Data Path :
-. Fast Image Read/Writes
-. 15ns Ultra Fast Page Mode(
t
UPC
) with EDO
4 Each BE and OE for Byte-Write/Read Control
Dual 128 Byte Split Serial Register
-. Dual Buffers Relax System Timing
-. 83MHz Serial Clock Frequency
5.0V
±
10% Supply Voltage
TTL I/O Level Compatible
120-Pin PQFP
GENERAL DESCRIPTION
FEATURES
PIN NAMES
Pin Name
SC
SE
SQ
0
-SQ
15
BE
0
-
3
OE
RAS
CAS
DSF 0, 1, 2
W
0
/DQ
0
~ W
31
/DQ
31
A
0
~ A
8
NC
V
CC
V
SS
Pin Function
Serial Clock
Serial Enable
Serial Data Output
Byte Enable
Output Enable
Row Address Strobe
Column Address Strobe
Special Function Pins
Data Write Mask/ Input-Output
Address Inputs
(No Connection)
Power
Ground
KEY TIMING PARAMETERS
Speed
Parameter
-50
-60
RAM read/write & block
ultra fast page cycle time(
t
UPC
)
15ns
20ns
RAS access time(
t
RAC
)
CAS access time(
t
CAC
)
RAS cycle time(
t
RC
)
SAM cycle time(
t
SCC
)
SAM access time(
t
SCA
)
SE access time(
t
SEA
)
I
DD
1 : RAM op. current
I
DD
2 : Stand-by current
I
DD
1A : RAM & SAM op. current
I
DD
2A : SAM op. current
50ns
12ns
90ns
12ns
10ns
12ns
180mA
10mA
210mA
50mA
60ns
12ns
110ns
14ns
13ns
12ns
160mA
10mA
190mA
45mA
PERFORMANCE
Graphic Operations
10-Pixel Vector
7 x 9 Character Draw
FILL
BitBLT(Vertical Scroll)
Cycle
UFW
UFW
UFBW8
UFBR/UFBWL 0.45 G Byte/Sec
Peak Performance
2.96 M Vector/Sec
1.5 M Character/Sec
2.1 G Byte/Sec
SAMSUNG ELECTRONICS CO.Ltd. reserves the right to change products and specifications without notice.
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