參數(shù)資料
型號: KM4232W259A
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: CMOS Window RAM(1M Byte Dual Ported DRAM Array)(CMOS視窗RAM(1M字節(jié)的雙口動態(tài)RAM陣列))
中文描述: 窗口的CMOS內(nèi)存(1M字節(jié)雙端口內(nèi)存陣列)(視窗的CMOS存儲器(100萬字節(jié)的雙口動態(tài)內(nèi)存陣列))
文件頁數(shù): 4/46頁
文件大?。?/td> 836K
代理商: KM4232W259A
KM4232W259A
CMOS WINDOW RAM
Rev.0 (August 1997)
C
D
DRAM Bit 31
DRAM Bit 30
DRAM Bit 2
DRAM Bit 1
DRAM Bit 0
The window RAM(WRAM
TM
) can be divided into four major
functional blocks(refer to block diagram). The DRAM array orga-
nized as 32 (512 x 512) bit planes, the Serial access mem-
ory(SAM), the Read/Write control blocks, and the color registers
and data latches block. The WRAM
TM
cycles can be divided into
two major categories, External Data transfer cycles and internal
Data transfer cycles.
FUNCTIONAL DESCRIPTION
Row DecoDRAM Bit 29
(512)
512 x 512
array
(32 each)
B
A
I/O S/A,
WDRV
ROW ADDRESS
COLUMN ADDRESS
REFRESH COUNTER
LOAD BLOCK
CONTROL
LOAD BLOCK
DEST(2 BITS)
8
8
LATCH 0
LATCH 1
LATCH 2
LATCH 3
COLOR 0
COLOR 1
BLOCK
SAM ARRAY
8 x 8 x 32
SERIAL
REGISTER
CONTROL
COUNTER
2
16
16
16
SERIAL
DATA
SQ0 ~ 15
SC
SE
B
B
WRITE BLOCK CONTROL
(RAS ENABLE, MUX)
WRITE BLOCK
SOURCE(2 BITS)
ADDRESS BUFFER
8
A
0
~ A
8
32
W/DQ
0
~
31
DATA BUFFER
2
32
256
256
256
256
9
9
9
8 : 1
MUX
256
R
B
O
B
D
C
D
D
9
Figure 2. BLOCK DIAGRAM
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