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參數(shù)資料
| 型號(hào)： | KM44C4105C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out(4M x 4位 CMOS 四CAS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
| 中文描述： | 4米× 4位的CMOS DRAM與中科院四擴(kuò)展數(shù)據(jù)輸出（4米× 4位的CMOS四中科院動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶擴(kuò)展數(shù)據(jù)輸出）） |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 363K |
| 代理商： | KM44C4105C |
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CMOS DRAM
KM44C4005C, KM44C4105C
AC CHARACTERISTICS
(Continued)
Parameter
Symbol
-5
-6
Units
Notes
Min
Max
Min
Max
Data set-up time
t
DS
t
DH
t
REF
t
REF
t
REF
t
WCS
t
CWD
t
RWD
t
AWD
t
CPWD
t
CSR
t
CHR
t
RPC
t
CPA
t
HPC
t
HPRWC
t
CP
t
RASP
t
RHCP
t
OEA
t
OED
t
OEZ
t
OEH
t
WTS
t
WTH
t
WRP
t
WRH
t
DOH
t
REZ
t
WEZ
t
WED
t
OCH
t
CHO
t
OEP
t
WPE
t
RASS
t
RPS
t
CHS
t
CLCH
0
0
ns
9
Data hold time
8
10
ns
9
Refresh period (2K, Normal)
32
32
ms
Refresh period (4K, Normal)
64
64
ms
Refresh period (L-ver)
128
128
ms
Write command set-up time
0
0
ns
7,18
CAS to W delay time
30
34
ns
7,16
RAS to W delay time
67
79
ns
7
Column address to W delay time
42
49
ns
7
CAS precharge to W delay time
47
54
ns
7
CAS set-up time (CAS -before-RAS refresh)
5
5
ns
18
CAS hold time (CAS -before-RAS refresh)
10
10
ns
17
RAS to CAS precharge time
5
5
ns
18
Access time from CAS precharge
28
35
ns
3,17
Hyper Page mode cycle time
20
24
ns
14,21
Hyper Page read-modify-write cycle time
62
71
ns
14,21
CAS precharge time (Hyper Page cycle)
8
10
ns
22
RAS pulse width (Hyper Page cycle)
50
200K
60
200K
ns
RAS hold time from CAS precharge
30
35
ns
OE access time
13
15
ns
23
OE to data delay
13
15
ns
24
Output buffer turn off delay time from OE
3
13
3
15
ns
6
OE command hold time
13
15
ns
Write command set-up time (Test mode in)
10
10
ns
11
Write command hold time (Test mode in)
10
10
ns
11
W to RAS precharge time(C-B-R refresh)
10
10
ns
W to RAS hold time(C-B-R refresh)
10
10
ns
Output data hold time
5
5
ns
Output buffer turn off delay from RAS
3
13
3
15
ns
6,13
Output buffer turn off delay from W
3
13
3
15
ns
6
W to data delay
15
15
ns
OE to CAS hold time
5
5
ns
CAS hold time to OE
5
5
ns
OE precharge time
5
5
ns
W pulse width (Hyper Page Cycle)
5
5
ns
RAS pulse width (C-B-R self refresh)
100
100
us
27,28,29
RAS precharge time (C-B-R self refresh)
90
110
ns
27,28,29
CAS hold time (C-B-R self refresh)
-50
-50
ns
27,28,29
Hold time CAS low to CAS high
5
5
ns
15,26
相關(guān)PDF資料 |
PDF描述 |
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| KM44C4103C | 4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode(4M x 4位CMOS四CAS 動(dòng)態(tài)RAM(帶快速頁(yè)模式)) |
| KM44C4003C | 4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode(4M x 4位CMOS四CAS 動(dòng)態(tài)RAM(帶快速頁(yè)模式)) |
| KM44C4104C | 4M x 4Bit CMOS Dynamic RAM with Extended Data Out(4M x 4位 CMOS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
| KM44C4004C | 4M x 4Bit CMOS Dynamic RAM with Extended Data Out(4M x 4位 CMOS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
| KM44V4004C | 4M x 4Bit CMOS Dynamic RAM with Extended Data Out(4M x 4位 CMOS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM44L16031BT-GFZ/Y/0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 0.61 |
| KM44L32031BT-G(F)0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 0.61 |
| KM44L32031BT-G(F)Y | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 0.61 |
| KM44L32031BT-G(F)Z | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 0.61 |
| KM44L32031BT-G(L)0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 1.0 |
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