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參數(shù)資料
| 型號： | KMM466F104CT1 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 64 DRAM SODIMM(1M x 64 動態(tài) RAM模塊) |
| 中文描述： | 100萬× 64內(nèi)存的SODIMM（100萬× 64動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 396K |
| 代理商： | KMM466F104CT1 |
DRAM MODULE
KMM466F104CT1-L
KMM466F124CT1-L
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V
IH
(min) and V
IL
(max) and are assumed to be 5ns
for all inputs.
Measured with a load equivalent to 1 TTL loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are not-restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If
t
RWD
≥
t
RWD
(min),
t
CWD
≥
t
CWD
(min),
t
AWD
≥
t
AWD
(min) and
t
CPWD
≥
t
CPWD
(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit access time
is controlled by
t
AA
.
t
ASC
≥
6ns, Assume t
T
=2.0ns
If RAS goes high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes high before RAS high going , the open circuit condition
of the output is achieved by RAS going.
t
ASC,
t
CAH
are referenced to the earlier CAS falling edge.
t
CP
is specified from the last CAS rising edge in the previous
cycle to the first CAS falling edge in the next cycle.
t
CWD
is referenced to the later CAS falling edge at word read-
modify-write cycle.
t
CWL
is specified from W falling edge to the earlier CAS rising
edge.
t
CSR
is referenced to earlier CAS falling low before RAS tra-
dition low.
If
t
RASS
≥
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh
mode, 4096 cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh
specification.
For distributed CAS-before-RAS with 15.6us interval CAS-
before-RAS should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specifi-
cation.
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