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參數(shù)資料
| 型號： | KMM466S823BT2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8Mx64 SDRAM SODIMM(8M x 64 動態(tài) RAM模塊) |
| 中文描述： | 8Mx64 SDRAM內(nèi)存的SODIMM（8米× 64動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 123K |
| 代理商： | KMM466S823BT2 |
144pin SDRAM SODIMM
KMM466S823BT2
REV. 6 June '98
REFER TO THE INDIVIDUAL COMPONENT, NOT THE WHOLE MODULE.
Parameter
Symbol
-0
Unit
Note
Min
Max
CLK cycle time
CAS latency=3
t
CC
10
1000
ns
1
CAS latency=2
13
CLK to valid output delay
CAS latency=3
t
SAC
7
ns
1,2
CAS latency=2
7
Output data hold time
CAS latency=3
t
OH
3
ns
2
CAS latency=2
3
CLK high pulse width
t
CH
3.5
ns
3
CLK low pulse width
t
CL
3.5
ns
3
Input setup time
t
SS
2.5
ns
3
Input hold time
t
SH
1
ns
3
CLK to output in Low-Z
t
SLZ
1
ns
2
CLK to output in Hi-Z
CAS latency=3
t
SHZ
7
ns
CAS latency=2
7
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
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