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參數(shù)資料
| 型號(hào)： | KMM466S924T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8Mx64 SDRAM SODIMM(8M x 64 動(dòng)態(tài) RAM模塊) |
| 中文描述： | 8Mx64 SDRAM內(nèi)存的SODIMM（8米× 64動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 121K |
| 代理商： | KMM466S924T |
SERIAL PRESENCE DETECT
SDRAM MODULE
KMM466S924T-F0
Organization : 8Mx64
Composition : 8Mx16*4
Used component part # : KM416S8030T-F10
# of banks in module : 1 Row
# of banks in component : 4 banks
Feature : 1,000mil height & double sided component
Refresh : 4K/64ms
Contents ;
Byte #
Function Described
Function Supported
Hex value
Note
-0
-0
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
12
0Ch
1
4
# of column address on this assembly
9
09h
1
5
# of module Rows on this assembly
1 Row
01h
6
Data width of this assembly
64 bits
40h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time @CAS latency of 3
10ns
A0h
2
10
SDRAM access time from clock @CAS latency of 3
7ns
70h
2
11
DIMM configuraion type
Non parity
00h
12
Refresh rate & type
15.625us, support self refresh
80h
13
Primary SDRAM width
x16
10h
14
Error checking SDRAM width
None
00h
15
Minimum clock delay for back-to-back random column address
t
CCD
= 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Non-buffered, non-registered
& redundant addressing
00h
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
13ns
D0h
2
24
SDRAM access time from clock @CAS latency of 2
7ns
70h
2
25
SDRAM cycle time @CAS latency of 1
-
00h
2
26
SDRAM access time from clock @CAS latency of 1
-
00h
2
27
Minimum row precharge time (=t
RP
)
24ns
18h
28
Minimum row active to row active delay (t
RRD
)
20ns
14h
29
Minimum RAS to CAS delay (=t
RCD
)
24ns
18h
30
Minimum activate precharge time (=t
RAS
)
50ns
32h
31
Module Row density
1 Row of 64MB
10h
32~61
Superset information (maybe used in future)
-
00h
62
SPD data revision code
2nd edition
01h
63
Checksum for bytes 0 ~ 62
-
F4h
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