- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373166 > KMM53232004BV (SAMSUNG SEMICONDUCTOR CO. LTD.) 32M x 32 DRAM SIMM(32M x 32 動(dòng)態(tài) RAM模塊) PDF資料下載
參數(shù)資料
| 型號(hào)： | KMM53232004BV |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32M x 32 DRAM SIMM(32M x 32 動(dòng)態(tài) RAM模塊) |
| 中文描述： | 32M的內(nèi)存上海藥物研究所× 32（32兆× 32動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 400K |
| 代理商： | KMM53232004BV |
DRAM MODULE
KMM53232004BV/BVG
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Symbol
-5
-6
Unit
Note
Min
Max
28
Min
Max
35
Access time from CAS precharge
Hyper page mode cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
W pulse width
t
CPA
t
HPC
t
CP
t
RASP
t
RHCP
t
WRP
t
WRH
t
DOH
t
REZ
t
WEZ
t
WED
t
WPE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
11
20
8
50
30
10
10
5
3
3
15
5
25
10
60
35
10
10
5
3
3
15
5
200K
200K
13
13
15
15
6,12
6
AC CHARACTERISTICS
(0
°
C
≤
T
A
≤
70
°
C, Vcc=5.0V
±
10%. See notes 1,2.)
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are
reference levels for measuring timing of input signals. Transi-
tion times are measured between V
IH
(min) and V
IL
(max) and
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves
the open circuit and is not referenced for V
OH
or V
OL
t
WCS
is
non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit access time
is controlled by
t
AA
.
t
ASC
≥
6ns, Assume t
T
=2.0ns.
If RAS goes high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes high before RAS high going , the open circuit condition
of the output is achieved by RAS going.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KMM5324000BSW | 4M x 32 DRAM SIMM(4M x 32 動(dòng)態(tài) RAM模塊) |
| KMM5324004BSW | 4M x 32 DRAM SIMM(4M x 32 動(dòng)態(tài) RAM模塊) |
| KMM5328004BSW | 8M x 32 DRAM SIMM(8M x 32 動(dòng)態(tài) RAM模塊) |
| KMM5361203C2WG | 1M x 36 DRAM SIMM using 1Mx16 and 1Mx4 Quad CAS, 1K Refresh |
| KMM5361205C2W | 1M x 36 DRAM SIMM using 1Mx16 and 4M Quad CAS EDO, 1K Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KMM53232004CK | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32M x 32 DRAM SIMM Using 16Mx4, 4K Refresh, 5V |
| KMM53232004CKG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32M x 32 DRAM SIMM Using 16Mx4, 4K Refresh, 5V |
| KMM5324000BSW | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 32 DRAM SIMM Using 4Mx16, 4K Refresh, 5V |
| KMM5324000BSWG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 32 DRAM SIMM Using 4Mx16, 4K Refresh, 5V |
| KMM5324000CK | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 32 DRAM SIMM using 4Mx4, 4K/2K Refresh, 5V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。