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參數(shù)資料
| 型號： | KMM965G256B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx64 SGRAM SODIMM(256Kx64 圖形RAM模塊) |
| 中文描述： | 256Kx64 SGRAM個SODIMM（256Kx64圖形內(nèi)存模塊） |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 129K |
| 代理商： | KMM965G256B |
SGRAM MODULE
KMM965G256BQ(P)N / KMM966G256BQ(P)N
- 2 -
Rev. 2.5 (Jul. 1998)
Revision History
Revision 2.5 (July 1998)
Added -7(143MHz) speed product.
Changed SPD data, Byte #62 from 02h to 00h.
Revision 2.4 (June 1998)
Added KMM965G256B product which does not support SPD.
Revision 2.3 (March 1998)
Changed the Current values of ICC1, ICC3N, ICC4, ICC7 in
DC CHARACTERISTICS.
Revision 2.2 (February 1998)
Removed KMM966G256B-H/12 product(-H : 100MHz @ CL =2, -12 : 83MHz @ CL=3).
Changed the Current values of ICC1, ICC4, ICC5, ICC6, ICC7 in
DC CHARACTERISTICS.
Changed tSAC from 6 to 6.5 @ 125MHz, tSS from 2 to 2.5 @ 125MHz in
AC PARAMETER
.
Changed SPD data according to each changed AC Parameters.
Delete a page including
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE.
Revision 2.1 (December 3, 1997)
Modified an erratum pin name of Pin #65 from CS1 to CS1, Pin #66 from CS0 to CS0, Pin #94 from ADD to VDD in
PIN
CONFIGURATIONS
- page 3.
Revision 2.0 (November 26, 1997)
Initial Draft --- Final Spec. (comply with Intel 0.2 spec. which is basically compatible with Intel 0.1 spec. except the
changed functionality of
Strapping Resistor
DQ31 from Memory Timing to CAS Latency - page 4.
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