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參數(shù)資料
| 型號： | KMM965G256B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx64 SGRAM SODIMM(256Kx64 圖形RAM模塊) |
| 中文描述： | 256Kx64 SGRAM個SODIMM（256Kx64圖形內(nèi)存模塊） |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 129K |
| 代理商： | KMM965G256B |
SGRAM MODULE
KMM965G256BQ(P)N / KMM966G256BQ(P)N
- 15
Rev. 2.5 (Jul. 1998)
SERIAL PRESENCE DETECT INFORMATION
Byte #
Function Described
Function Supported
Hex value
Note
-7
-8
-10
-7
-8
-10
0
# of bytes written into serial memory at module manufacturer
128byte
80h
1
Total # of bytes of SPD memory device
256bytes (2K bit)
08h
2
Fundamental memory type
SGRAM
06h
TBD
3
# of row address on this assembly
9
09h
1
4
# of column address on this assembly
8
08h
1
5
# of module banks on this assembly
1 bank
01h
6
Data width of this assembly
64 bits
40h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SGRAM cycle time from clock @CAS latency of 3
7ns
8ns
10ns
70h
A0h
2
10
SGRAM access time from clock @CAS latency of 3
6ns
6.5ns
7ns
60h
65h
70h
2
11
DIMM configuraion type
Non parity
00h
12
Refresh rate & type
15.625us, support self refresh
80h
13
Primary SGRAM width
x32
20h
14
Error checking SGRAM width
None
00h
15
Minimum clock delay for back-to-back random column address
t
CCD
= 1CLK
01h
16
SGRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SGRAM device attributes : # of banks on SGRAM device
2 banks
02h
18
SGRAM device attributes : CAS latency
2 & 3
06h
19
SGRAM device attributes : CS latency
0 CLK
01h
20
SGRAM device attributes : Write latency
0 CLK
01h
21
SGRAM module attributes
Non-buffered, non-registered
& redundant addressing
00h
22
SGRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
4Eh
23
SGRAM cycle time @CAS latency of 2
12ns
12ns
13ns
C0h
C0h
D0h
2
24
SGRAM access time @CAS latency of 2
8ns
8ns
9ns
80h
80h
90h
2
25
SGRAM cycle time @CAS latency of 1
-
-
-
00h
00h
00h
2
26
SGRAM access time @CAS latency of 1
-
-
-
00h
00h
00h
2
27
Minimum row precharge time (=t
RP
)
21ns
20ns
20ns
15h
14h
14h
2
28
Minimum row active to row active delay (t
RRD
)
14ns
16ns
20ns
0Eh
10h
14h
2
29
Minimum RAS to CAS delay (=t
RCD
)
16ns
16ns
20ns
10h
10h
14h
2
30
Minimum activate to precharge time (=t
RAS
)
49ns
48ns
50ns
31h
30h
32h
2
31
Module bank density
1 bank of 2MB
80h
TBD
32
Address and Command signal Input setup time (=tSS)
2ns
2.5ns
2.5ns
20h
25h
25h
2
33
Address and Command signal Input hold time (=tSH)
1ns
1ns
1ns
10h
10h
10h
2
34
Data signal Input setup time (=tSS)
2ns
2.5ns
2.5ns
20h
25h
25h
2
Serial PD Interface Protocol : I
2
C
Current sink capability of SDA driver
≤
3mA
Maximum clock frequency : 80KHz
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