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參數(shù)資料
| 型號(hào)： | KMM965G256B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx64 SGRAM SODIMM(256Kx64 圖形RAM模塊) |
| 中文描述： | 256Kx64 SGRAM個(gè)SODIMM（256Kx64圖形內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 11/15頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | KMM965G256B |
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SGRAM MODULE
KMM965G256BQ(P)N / KMM966G256BQ(P)N
- 12
Rev. 2.5 (Jul. 1998)
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note
: 1. If A
9
is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. The full column burst(256bit) is available only at Sequential mode of burst type.
3. If LC and LM both high(1), data of mask and color register will be unknown.
Register Programmed with MRS
(Note 1)
Address
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Function
W.B.L
TM
CAS Latency
BT
Burst Length
(Note 2)
Test Mode
CAS Latency
Burst Type
Burst Length
A
8
A
7
Type
A
6
A
5
A
4
Latency
A
3
Type
A
2
A
1
A
0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
Reserved
0
1
Vendor
Use
Only
0
0
1
-
1
Interleave
0
0
1
2
Reserved
1
0
0
1
0
2
0
1
0
4
4
1
1
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
A
9
Length
1
0
1
Reserved
1
0
1
Reserved
Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
256(Full)
Reserved
Special Mode Register Programmed with SMRS
Address
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Function
X
LC
LM
X
(Note 3)
Load Color
Load Mask
A
6
Function
A
5
Function
0
Disable
0
Disable
1
Enable
1
Enable
MODE REGISTER FIELD TABLE TO PROGRAM MODES
POWER UP SEQUENCE
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