參數(shù)資料
型號: KS16112
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: CAP 33PF 50V 5% NPO(C0G) SMD-0603 TR-7-PA
中文描述: 14400分之9600基點傳真調(diào)制解調(diào)器
文件頁數(shù): 33/69頁
文件大?。?/td> 513K
代理商: KS16112
KS16112/4
9600/14400 bps FAX MODEM
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33
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The TD3 bit is set when the modem detects energy above the turn on threshold of tone detector No. 3.
As the default, tone detector No. 3 is programmed to detect energy in the 462Hz
±
14Hz frequency range.
All three tone detectors ( TD1, TD2 and TD3 ) have host programmable filter coefficients.
Tone detector No. 3 is operational in FSK, FSK and DTMF receiver and Tone configurations and whenever
the modem is not transmitting. TD3 serves as the output status indicator when the CASC bit is set forming
a 12th order filter using TD1, TD2, and TD3 ( see CASC bit description ).
When the host sets the TRND bit while in the receive mode, the modem will not recognize the training
sequence and will not enter the training state. In the transmit mode, the modem will not transmit the training
sequence when the RTS input is active or the RTSB bit is set.
When the WT1 control bit is set, the modem reads 16 bits of data from the Y RAM Data 1 registers ( YDM 1,
YDL 1 ) and writes it into its internal RAM as addressed by ADR1 and CRAM1 immediately following the
host setting the RA1 control bit. If the MSB of ADR1 is a zero, the data is copied into X RAM, if the MSB
of ADR1 is a one, the data is copied into Y RAM. When WT1 is reset the modem reads real and imaginary
16 - bit data from its internal RAM locations as addressed by ADR1 and CRAM1 and writes it into the
X RAM Data 1 registers ( XDM1, XDL1 ) and Y RAM Data 1 registers ( YDM1, YDL1 ) immediately after the
host sets the RA1 control bit.
WT1
RAM Write 1
05 : 1 ( 0 )
TRND
Training Disable
07 : 6( 0 )
TD3
Tone Detector No.3
08 : 7( - )
When the WT2 control bit is set, the modem reads 16 bits of data from the Y RAM Data 2 registers ( YDM1,
YDL1 ) and writes it into its internal RAM as addressed by ADR2 and CRAM2 immediately following the
host setting the RA2 control bit. If the MSB of ADR2 is a zero, the data is copied into X RAM. If the MSB
of ADR2 is a one, the data is copied into Y RAM. When WT2 is reset, the modem reads real and
imaginary 16bits data from its internal RAM locations as addressed by ADR2 and CRAM2 and writes it into
the X RAM Data 1 registers ( XDM1, XDL1 ) and Y RAM Data 1 registers ( YDM1, YDL1 ) immediately after
the host sets the RA2 control bit.
WT2
RAM Write 2
15 : 1 ( 0 )
XDL1 contains the least significant byte of the 16-bit X RAM1 Data word used while reading XRAM locations.
XDL2
X RAM Data 2 LSB
12 : 0 - 7 ( - )
XDL1
X RAM Data 1 LSB
02 : 0 - 7 ( - )
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