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| 型號： | KSZ8051MLLI TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 28/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX PHY 10/T100 3.3V MII 48LQFP |
| 特色產(chǎn)品： | KSZ8051/8031/8021 Series |
| 標準包裝： | 1 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 標準包裝 |
| 配用： | 576-3864-ND - BOARD EVALUATION FOR KSZ8051MLL |
| 其它名稱： | 576-3888-6 |
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MCP4017/18/19
DS22147A-page 34
2009 Microchip Technology Inc.
5.2
I2C Bit Definitions
I2C bit definitions include:
Figure 5-8 shows the waveform for these states.
5.2.1
START BIT
The Start bit (see Figure 5-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “High”.
FIGURE 5-2:
Start Bit.
5.2.2
DATA BIT
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see Figure 5-3).
FIGURE 5-3:
Data Bit.
5.2.3
ACKNOWLEDGE (A) BIT
The A bit (see Figure 5-4) is a response from the Slave
device to the Master device. Depending on the context
of the transfer sequence, the A bit may indicate
different things. Typically the Slave device will supply
an A response after the Start bit and 8 “data” bits have
been received. The A bit will have the SDA signal low.
FIGURE 5-4:
Acknowledge Waveform.
If the Slave Address is not valid, the Slave Device will
issue a Not A (A). The A bit will have the SDA signal
high.
If an error condition occurs (such as an A instead of A)
then an START bit must be issued to reset the
command state machine.
TABLE 5-1:
MCP4017/18/19 A / A
RESPONSES
5.2.4
REPEATED START BIT
The Repeated Start bit (see Figure 5-5) indicates the
current
Master
Device
wishes
to
continue
communicating with the current Slave Device without
releasing the I2C bus. The Repeated Start condition is
the same as the Start condition, except that the
Repeated Start bit follows a Start bit (with the Data bits
+ A bit) and not a Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 5-5:
Repeat Start Condition
Waveform.
SDA
SCL
S
1st Bit
2nd Bit
SDA
SCL
S
1st Bit
2nd Bit
A
8
D0
9
SDA
SCL
Event
Acknowledge
Bit Response
Comment
General Call
A
Slave Address
valid
A
Slave Address
not valid
A
Bus Collision
N.A.
I2C Module Resets,
or a “Don’t Care” if
the collision occurs
on the Masters
“Start bit”.
Note 1: A bus collision during the Repeated Start
condition occurs if:
SDA is sampled low when SCL goes
from low to high.
SCL goes low before SDA is asserted
low. This may indicate that another mas-
ter is attempting to transmit a data "1".
SDA
SCL
Sr = Repeated Start
1st Bit
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| KSZ8051MNL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver w/ MII Support (32-QFN) - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
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