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參數(shù)資料
| 型號： | KSZ8051MLLI TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 31/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX PHY 10/T100 3.3V MII 48LQFP |
| 特色產(chǎn)品： | KSZ8051/8031/8021 Series |
| 標準包裝： | 1 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 標準包裝 |
| 配用： | 576-3864-ND - BOARD EVALUATION FOR KSZ8051MLL |
| 其它名稱： | 576-3888-6 |
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2009 Microchip Technology Inc.
DS22147A-page 37
MCP4017/18/19
5.3
Software Reset Sequence
At times it may become necessary to perform a
Software Reset Sequence to ensure the MCP4017/18/
19 device is in a correct and known I2C Interface state.
This only resets the I2C state machine.
This is useful if the MCP4017/18/19 device powers up
in an incorrect state (due to excessive bus noise, etc),
or if the Master Device is reset during communication.
Figure 5-11 shows the communication sequence to
software reset the device.
FIGURE 5-11:
Software Reset Sequence
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device.In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP4017/18/19 is driving an A
on the I2C bus, or is in output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP4017/18/19 holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see a A (the Master Device does not
drive the I2C bus low to acknowledge the data sent by
the MCP4017/18/19), which also forces the MCP4017/
18/19 to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP4017/18/19, AND then as the Master Device
returns to normal operation and issues a Start condition
while the MCP4017/18/19 is issuing an A. In this case
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP4017/18/19 could initiate a write cycle.
The Stop bit terminates the current I2C bus activity. The
MCP4017/18/19 wait to detect the next Start condition.
This sequence does not effect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
5.4
Serial Commands
The MCP4017/18/19 devices support 2 serial
commands. These commands are:
Note:
This technique should be supported by
any I2C compliant device. The 24xxxx I2C
Serial EEPROM devices support this tech-
nique, which is documented in AN1028.
Note:
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP4017/18/19.
S
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
S
P
Start
bit
Nine bits of ‘1’
Start bit
Stop bit
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