參數(shù)資料
型號(hào)： KSZ8051MNLI
廠商： Micrel Inc
文件頁(yè)數(shù)： 15/59頁(yè)
文件大?。?/td> 0K
描述： TXRX PHY 10/T100 3.3V 32QFN
標(biāo)準(zhǔn)包裝： 640
類型： PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： MII
電源電壓： 1.8V，2.5V，3.3V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN（5x5）
包裝： 托盤
配用： 576-3865-ND - BOARD EVALUATION FOR KSZ8051MNL
其它名稱： 576-3845
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
22
M9999-070910-1.0
MII Signal Definition
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
MII
Signal Name
Direction
(with respect to PHY,
KSZ8051MNL signal)
Direction
(with respect to MAC)
Description
TXC
Output
Input
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN
Input
Output
Transmit Enable
TXD[3:0]
Input
Output
Transmit Data [3:0]
RXC
Output
Input
Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXDV
Output
Input
Receive Data Valid
RXD[3:0]
Output
Input
Receive Data [3:0]
RXER
Output
Input, or (not required)
Receive Error
CRS
Output
Input
Carrier Sense
COL
Output
Input
Collision Detection
Table 1. MII Signal Definition
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle, or link is down.
In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains
asserted until the end of the frame.
In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
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